Symbol: PIPE_A
sys/dev/pci/drm/i915/display/g4x_dp.c
1392
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/g4x_dp.c
271
*pipe = PIPE_A;
sys/dev/pci/drm/i915/display/g4x_dp.c
441
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_dp.c
442
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_dp.c
446
intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
sys/dev/pci/drm/i915/display/g4x_dp.c
455
intel_wait_for_vblank_if_active(display, PIPE_A);
sys/dev/pci/drm/i915/display/g4x_dp.c
456
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/g4x_dp.c
457
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
403
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
404
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
407
temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
421
intel_wait_for_vblank_if_active(display, PIPE_A);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
422
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
423
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
748
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/hsw_ips.c
189
return HAS_IPS(display) && crtc->pipe == PIPE_A;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1898
case PIPE_A:
sys/dev/pci/drm/i915/display/i9xx_wm.c
293
case PIPE_A:
sys/dev/pci/drm/i915/display/i9xx_wm.c
3369
if (dirty & WM_DIRTY_PIPE(PIPE_A))
sys/dev/pci/drm/i915/display/i9xx_wm.c
3370
intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3674
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3681
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3682
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3714
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3717
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3718
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3719
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3745
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3746
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3747
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3758
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3759
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3760
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
817
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
sys/dev/pci/drm/i915/display/i9xx_wm.c
823
FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
824
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
sys/dev/pci/drm/i915/display/i9xx_wm.c
867
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
sys/dev/pci/drm/i915/display/i9xx_wm.c
869
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
870
FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
871
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
sys/dev/pci/drm/i915/display/i9xx_wm.c
893
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
894
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
895
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
sys/dev/pci/drm/i915/display/i9xx_wm.c
905
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
906
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
907
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
sys/dev/pci/drm/i915/display/icl_dsi.c
1744
*pipe = PIPE_A;
sys/dev/pci/drm/i915/display/icl_dsi.c
834
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_backlight.c
1417
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
sys/dev/pci/drm/i915/display/intel_backlight.c
189
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
sys/dev/pci/drm/i915/display/intel_color.c
3985
if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)
sys/dev/pci/drm/i915/display/intel_crt.c
1065
crt->base.pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_crt.c
1131
FDI_RX_CTL(PIPE_A)) & fdi_config;
sys/dev/pci/drm/i915/display/intel_crt.c
255
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_crt.c
284
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/intel_crt.c
296
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_crt.c
341
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/intel_cursor.c
301
intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);
sys/dev/pci/drm/i915/display/intel_cursor.c
302
intel_de_write_fw(display, CURBASE(display, PIPE_A), base);
sys/dev/pci/drm/i915/display/intel_cursor.c
303
intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);
sys/dev/pci/drm/i915/display/intel_cursor.c
304
intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
sys/dev/pci/drm/i915/display/intel_cursor.c
305
intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);
sys/dev/pci/drm/i915/display/intel_cursor.c
311
intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
sys/dev/pci/drm/i915/display/intel_cursor.c
330
power_domain = POWER_DOMAIN_PIPE(PIPE_A);
sys/dev/pci/drm/i915/display/intel_cursor.c
335
ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;
sys/dev/pci/drm/i915/display/intel_cursor.c
337
*pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_ddi.c
2483
return BIT(PIPE_A) | BIT(PIPE_B);
sys/dev/pci/drm/i915/display/intel_ddi.c
2485
return BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_ddi.c
4458
if (display->platform.haswell && crtc->pipe == PIPE_A &&
sys/dev/pci/drm/i915/display/intel_ddi.c
554
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_ddi.c
832
*pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_display.c
2185
(crtc->pipe == PIPE_A || display->platform.i915g);
sys/dev/pci/drm/i915/display/intel_display.c
3443
pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
sys/dev/pci/drm/i915/display/intel_display.c
3763
trans_pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_display.c
8327
intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
sys/dev/pci/drm/i915/display/intel_display_device.c
1074
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
1163
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
sys/dev/pci/drm/i915/display/intel_display_device.c
1341
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
sys/dev/pci/drm/i915/display/intel_display_device.c
1364
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
171
[PIPE_A] = CURSOR_A_OFFSET, \
sys/dev/pci/drm/i915/display/intel_display_device.c
176
[PIPE_A] = CURSOR_A_OFFSET, \
sys/dev/pci/drm/i915/display/intel_display_device.c
1796
display_runtime->num_scalers[PIPE_A] = 2;
sys/dev/pci/drm/i915/display/intel_display_device.c
182
[PIPE_A] = CURSOR_A_OFFSET, \
sys/dev/pci/drm/i915/display/intel_display_device.c
1820
display_runtime->num_sprites[PIPE_A] = 2;
sys/dev/pci/drm/i915/display/intel_display_device.c
1866
display_runtime->pipe_mask &= ~BIT(PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_device.c
189
[PIPE_A] = CURSOR_A_OFFSET, \
sys/dev/pci/drm/i915/display/intel_display_device.c
196
[PIPE_A] = CURSOR_A_OFFSET, \
sys/dev/pci/drm/i915/display/intel_display_device.c
242
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
255
.__runtime_defaults.pipe_mask = BIT(PIPE_A), \
sys/dev/pci/drm/i915/display/intel_display_device.c
305
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
394
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
451
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
sys/dev/pci/drm/i915/display/intel_display_device.c
480
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
505
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
534
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/intel_display_device.c
582
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
635
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
655
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
679
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/intel_display_device.c
829
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
sys/dev/pci/drm/i915/display/intel_display_device.c
904
.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
sys/dev/pci/drm/i915/display/intel_display_device.c
996
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
sys/dev/pci/drm/i915/display/intel_display_irq.c
1285
pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1765
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_display_irq.c
1916
i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1930
i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1931
i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1965
i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
sys/dev/pci/drm/i915/display/intel_display_irq.c
394
i915_enable_pipestat(display, PIPE_A,
sys/dev/pci/drm/i915/display/intel_display_irq.c
543
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_display_irq.c
698
intel_pch_fifo_underrun_irq_handler(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_irq.c
707
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_display_irq.c
828
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_display_limits.h
34
TRANSCODER_A = PIPE_A,
sys/dev/pci/drm/i915/display/intel_display_power.c
1809
u32 status = intel_de_read(display, DPLL(display, PIPE_A));
sys/dev/pci/drm/i915/display/intel_display_power.h
121
((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A))
sys/dev/pci/drm/i915/display/intel_display_power.h
123
((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A))
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1336
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1493
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1654
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_map.c
1736
.irq_pipe_mask = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1093
if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1094
i830_enable_pipe(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1103
i830_disable_pipe(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1109
return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1249
if (pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1534
assert_pll_disabled(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1689
enum pipe pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1720
enum pipe pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
40
DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
46
DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
sys/dev/pci/drm/i915/display/intel_display_regs.h
1993
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
sys/dev/pci/drm/i915/display/intel_dmc.c
253
#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
sys/dev/pci/drm/i915/display/intel_dmc.c
475
for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
sys/dev/pci/drm/i915/display/intel_dmc.c
492
MTL_PIPEDMC_GATING_DIS(PIPE_A) |
sys/dev/pci/drm/i915/display/intel_dmc.c
905
PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
288
#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
693
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
707
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_dpll.c
1429
if (crtc->pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
1455
if (crtc->pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
1959
if (pipe == PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
1965
if (pipe == PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
2164
if (pipe != PIPE_A) {
sys/dev/pci/drm/i915/display/intel_dpll.c
2238
if (pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
2256
if (pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_dpll.c
400
if (display->platform.cherryview && crtc->pipe != PIPE_A)
sys/dev/pci/drm/i915/display/intel_fdi.c
221
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_fdi.c
420
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_fdi.c
867
intel_de_write(display, FDI_RX_MISC(PIPE_A),
sys/dev/pci/drm/i915/display/intel_fdi.c
877
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/pci/drm/i915/display/intel_fdi.c
878
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/display/intel_fdi.c
883
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/pci/drm/i915/display/intel_fdi.c
912
intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
sys/dev/pci/drm/i915/display/intel_fdi.c
916
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/pci/drm/i915/display/intel_fdi.c
917
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/display/intel_fdi.c
923
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
sys/dev/pci/drm/i915/display/intel_fdi.c
925
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
sys/dev/pci/drm/i915/display/intel_fdi.c
947
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/pci/drm/i915/display/intel_fdi.c
948
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/display/intel_fdi.c
960
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
sys/dev/pci/drm/i915/display/intel_fdi.c
963
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
sys/dev/pci/drm/i915/display/intel_fdi.c
984
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
sys/dev/pci/drm/i915/display/intel_fdi.c
988
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
sys/dev/pci/drm/i915/display/intel_fdi.c
991
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
sys/dev/pci/drm/i915/display/intel_fdi.c
992
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
137
u32 bit = (pipe == PIPE_A) ?
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
201
u32 bit = (pch_transcoder == PIPE_A) ?
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
666
enum pipe pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_pch_display.c
124
(val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
sys/dev/pci/drm/i915/display/intel_pch_display.c
132
val |= SDVO_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
143
(val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
sys/dev/pci/drm/i915/display/intel_pch_display.c
151
val |= DP_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
29
(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
37
return PIPE_A;
sys/dev/pci/drm/i915/display/intel_pch_display.c
555
assert_fdi_rx_enabled(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
557
val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));
sys/dev/pci/drm/i915/display/intel_pch_display.c
563
intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
589
intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
sys/dev/pci/drm/i915/display/intel_pch_display.c
599
assert_pch_transcoder_disabled(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
604
ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
630
tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/display/intel_pfit.c
90
max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
177
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
238
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
315
pipe_config->hw.active && crtc->pipe == PIPE_A &&
sys/dev/pci/drm/i915/display/intel_pps.c
1178
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
sys/dev/pci/drm/i915/display/intel_pps.c
1270
if (pipe != PIPE_A && pipe != PIPE_B)
sys/dev/pci/drm/i915/display/intel_pps.c
1273
if (pipe != PIPE_A && pipe != PIPE_B)
sys/dev/pci/drm/i915/display/intel_pps.c
1274
pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_pps.c
174
unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
sys/dev/pci/drm/i915/display/intel_pps.c
231
pipe = PIPE_A;
sys/dev/pci/drm/i915/display/intel_pps.c
302
for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
sys/dev/pci/drm/i915/display/intel_pps.c
46
case PIPE_A:
sys/dev/pci/drm/i915/display/intel_psr.c
1212
return pipe == PIPE_A && port == PORT_A;
sys/dev/pci/drm/i915/display/intel_psr.c
1660
if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
sys/dev/pci/drm/i915/display/intel_sdvo.c
1864
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1865
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1868
temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1874
intel_wait_for_vblank_if_active(display, PIPE_A);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1875
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1876
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
sys/dev/pci/drm/i915/display/intel_vdsc.c
393
pipe == PIPE_A)
sys/dev/pci/drm/i915/display/intel_vdsc.c
51
drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
sys/dev/pci/drm/i915/display/intel_vga.c
62
pipe = PIPE_A;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2409
return pipe - PIPE_A + INTEL_FBC_A;
sys/dev/pci/drm/i915/display/skl_watermark.c
1006
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1008
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1022
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1024
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
1039
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
1041
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
sys/dev/pci/drm/i915/display/skl_watermark.c
1053
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
1055
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1067
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
1069
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1080
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1082
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1094
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
1096
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1108
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1110
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1122
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1124
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1137
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1139
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
1153
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
1155
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
3345
case PIPE_A:
sys/dev/pci/drm/i915/display/skl_watermark.c
3347
active_pipes &= BIT(PIPE_A) | BIT(PIPE_D);
sys/dev/pci/drm/i915/display/skl_watermark.c
750
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
752
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
762
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
764
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
775
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
777
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
789
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
791
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
813
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
815
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
825
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
827
[PIPE_A] = BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
838
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
840
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
852
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
854
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
866
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
868
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
880
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
882
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
895
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
897
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
911
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
913
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
924
.active_pipes = BIT(PIPE_A),
sys/dev/pci/drm/i915/display/skl_watermark.c
926
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
936
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
sys/dev/pci/drm/i915/display/skl_watermark.c
938
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
949
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
951
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
963
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
sys/dev/pci/drm/i915/display/skl_watermark.c
965
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/skl_watermark.c
977
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
979
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
sys/dev/pci/drm/i915/display/skl_watermark.c
991
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
sys/dev/pci/drm/i915/display/skl_watermark.c
993
[PIPE_A] = BIT(DBUF_S1),
sys/dev/pci/drm/i915/display/vlv_dsi.c
1963
encoder->pipe_mask = BIT(PIPE_A);
sys/dev/pci/drm/i915/display/vlv_dsi.c
997
*pipe = port == PORT_A ? PIPE_A : PIPE_B;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1293
[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1295
[2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1349
info->pipe = PIPE_A;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1362
info->pipe = PIPE_A;
sys/dev/pci/drm/i915/gvt/display.c
59
pipe = PIPE_A;
sys/dev/pci/drm/i915/gvt/display.c
642
[PIPE_A] = PIPE_A_VBLANK,
sys/dev/pci/drm/i915/gvt/display.c
648
if (pipe < PIPE_A || pipe > PIPE_C)
sys/dev/pci/drm/i915/gvt/display.c
90
pipe < PIPE_A || pipe >= I915_MAX_PIPES))
sys/dev/pci/drm/i915/gvt/handlers.c
1022
calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
sys/dev/pci/drm/i915/gvt/handlers.c
1046
calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
sys/dev/pci/drm/i915/gvt/handlers.c
2302
MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2303
MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
sys/dev/pci/drm/i915/gvt/handlers.c
2311
MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2312
MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
sys/dev/pci/drm/i915/gvt/handlers.c
2337
MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2340
MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
sys/dev/pci/drm/i915/gvt/handlers.c
2343
MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
sys/dev/pci/drm/i915/gvt/handlers.c
2490
MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
sys/dev/pci/drm/i915/gvt/handlers.c
2492
MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
sys/dev/pci/drm/i915/gvt/handlers.c
2494
MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
sys/dev/pci/drm/i915/gvt/handlers.c
2634
MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2635
MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2641
MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2642
MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2648
MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2649
MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
sys/dev/pci/drm/i915/gvt/handlers.c
2655
MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2656
MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2657
MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2658
MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2670
MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2674
MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2675
MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2676
MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2686
MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2690
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2691
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2692
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2693
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2705
MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2706
MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2707
MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2708
MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2720
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2721
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2722
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
2723
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
sys/dev/pci/drm/i915/gvt/handlers.c
708
vgpu->id, pipe_name(PIPE_A), new_rate);
sys/dev/pci/drm/i915/gvt/handlers.c
908
calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
sys/dev/pci/drm/i915/gvt/handlers.c
911
calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
sys/dev/pci/drm/i915/gvt/handlers.c
914
calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
sys/dev/pci/drm/i915/gvt/interrupt.c
508
DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
sys/dev/pci/drm/i915/gvt/reg.h
68
(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
sys/dev/pci/drm/i915/gvt/reg.h
78
(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
sys/dev/pci/drm/i915/intel_clock_gating.c
322
intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
sys/dev/pci/drm/i915/intel_clock_gating.c
433
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
sys/dev/pci/drm/i915/intel_clock_gating.c
481
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1003
MMIO_D(CUR_WM_TRANS(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1006
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1007
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1008
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1009
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 3));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1018
MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1019
MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1020
MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1021
MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1030
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1031
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1032
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1033
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1042
MMIO_D(PLANE_CTL(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1045
MMIO_D(PLANE_SURF(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1087
MMIO_D(PLANE_KEYVAL(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1090
MMIO_D(PLANE_KEYMAX(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
1093
MMIO_D(PLANE_KEYMSK(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
137
MMIO_D(PIPEDSL(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
145
MMIO_D(PIPESTAT(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
149
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
153
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
157
MMIO_D(CURCNTR(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
160
MMIO_D(CURPOS(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
163
MMIO_D(CURBASE(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
166
MMIO_D(CUR_FBC_CTL(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
176
MMIO_D(DSPCNTR(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
177
MMIO_D(DSPADDR(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
178
MMIO_D(DSPSTRIDE(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
179
MMIO_D(DSPPOS(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
180
MMIO_D(DSPSIZE(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
181
MMIO_D(DSPSURF(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
182
MMIO_D(DSPOFFSET(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
183
MMIO_D(DSPSURFLIVE(display, PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
184
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
203
MMIO_D(SPRCTL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
204
MMIO_D(SPRLINOFF(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
205
MMIO_D(SPRSTRIDE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
206
MMIO_D(SPRPOS(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
207
MMIO_D(SPRSIZE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
208
MMIO_D(SPRKEYVAL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
209
MMIO_D(SPRKEYMSK(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
210
MMIO_D(SPRSURF(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
211
MMIO_D(SPRKEYMAX(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
212
MMIO_D(SPROFFSET(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
213
MMIO_D(SPRSCALE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
214
MMIO_D(SPRSURFLIVE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
215
MMIO_D(REG_50080(PIPE_A, PLANE_SPRITE0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
309
MMIO_D(PF_CTL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
310
MMIO_D(PF_WIN_SZ(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
311
MMIO_D(PF_WIN_POS(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
312
MMIO_D(PF_VSCALE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
313
MMIO_D(PF_HSCALE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
324
MMIO_D(WM0_PIPE_ILK(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
343
MMIO_D(FDI_RX_IIR(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
346
MMIO_D(FDI_RX_IMR(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
349
MMIO_D(FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
374
MMIO_D(TRANS_DP_CTL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
377
MMIO_D(TVIDEO_DIP_CTL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
378
MMIO_D(TVIDEO_DIP_DATA(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
379
MMIO_D(TVIDEO_DIP_GCP(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
439
MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
440
MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
441
MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
442
MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
443
MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
444
MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
445
MMIO_D(PIPE_CSC_MODE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
446
MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
447
MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
448
MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
449
MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
450
MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
451
MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
478
MMIO_D(PREC_PAL_INDEX(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
479
MMIO_D(PREC_PAL_DATA(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
480
MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
492
MMIO_D(WM_LINETIME(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
514
MMIO_D(GAMMA_MODE(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
549
MMIO_D(HSW_AUD_CFG(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
551
MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
709
MMIO_F(LGC_PALETTE(PIPE_A, 0), 1024);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
761
MMIO_D(GEN8_DE_PIPE_IMR(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
762
MMIO_D(GEN8_DE_PIPE_IER(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
763
MMIO_D(GEN8_DE_PIPE_IIR(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
764
MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
812
MMIO_D(PIPE_MISC(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
831
MMIO_D(CHICKEN_PIPESL_1(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
949
MMIO_D(SKL_PS_WIN_POS(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
950
MMIO_D(SKL_PS_WIN_POS(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
955
MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
956
MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
961
MMIO_D(SKL_PS_CTRL(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
962
MMIO_D(SKL_PS_CTRL(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
967
MMIO_D(PLANE_BUF_CFG(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
968
MMIO_D(PLANE_BUF_CFG(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
969
MMIO_D(PLANE_BUF_CFG(PIPE_A, 2));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
970
MMIO_D(PLANE_BUF_CFG(PIPE_A, 3));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
979
MMIO_D(CUR_BUF_CFG(PIPE_A));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
982
MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
983
MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
984
MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
991
MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8);
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
994
MMIO_D(PLANE_WM_TRANS(PIPE_A, 0));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
995
MMIO_D(PLANE_WM_TRANS(PIPE_A, 1));
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
996
MMIO_D(PLANE_WM_TRANS(PIPE_A, 2));