sys/dev/pci/drm/i915/display/skl_universal_plane.c

2801

plane_ctl &= ~PLANE_CTL_TILED_MASK;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3062

tiling = val & PLANE_CTL_TILED_MASK;

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

84

#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

85

#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

86

#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

87

#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

88

#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

230

plane->tiled = val & PLANE_CTL_TILED_MASK;