PLANE_CTL
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));
intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);
val = intel_de_read(display, PLANE_CTL(pipe, plane_id));
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
MMIO_D(PLANE_CTL(PIPE_A, 2));
MMIO_D(PLANE_CTL(PIPE_B, 2));
MMIO_D(PLANE_CTL(PIPE_C, 2));