sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1014

!update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1017

update_state->pg_pipe_res_update[PG_DPP][j] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1050

if (j == PG_DPP && new_pipe->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1077

if (j == PG_DPP &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1130

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1137

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1145

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1148

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1199

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1219

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1282

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1311

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1341

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

959

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

975

update_state->pg_pipe_res_update[PG_DPP][j] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

115

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

172

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

47

!update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

50

update_state->pg_pipe_res_update[PG_DPP][j] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

67

update_state->pg_pipe_res_update[PG_DPP][i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

70

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

234

pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

480

pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled;