sys/dev/pci/drm/i915/display/intel_display_irq.c

304

enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |

sys/dev/pci/drm/i915/display/intel_display_irq.c

507

PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

539

status_mask = PIPE_FIFO_UNDERRUN_STATUS;

sys/dev/pci/drm/i915/display/intel_display_irq.c

596

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

620

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

646

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

102

if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

106

intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

125

enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

128

if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)