PHY_REG
ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431);
ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204);
ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
PHY_REG(BM_PORT_CTRL_PAGE, 17),
PHY_REG(BM_PORT_CTRL_PAGE, 17),
ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1),
em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
em_read_phy_reg(hw, PHY_REG(776, 20), &data);
ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data);
ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00);
PHY_REG(769, 17) /* Port General Configuration */
PHY_REG(769, 25) /* Rate Adapter Control Register */
PHY_REG(770, 16) /* KMRN FIFO's control/status register */
PHY_REG(770, 17) /* KMRN Power Management Control Register */
PHY_REG(770, 18) /* KMRN Inband Control Register */
PHY_REG(770, 19) /* KMRN Diagnostic register */
PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
PHY_REG(776, 18) /* Voltage regulator control register */
PHY_REG(776, 19) /* IGP3 Capability Register */
#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
#define CV_SMB_CTRL PHY_REG(769, 23)
#define I218_ULP_CONFIG1 PHY_REG(779, 16)
#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
#define HV_SCC_LOWER PHY_REG(778, 17)
#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
#define HV_ECOL_LOWER PHY_REG(778, 19)
#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
#define HV_MCC_LOWER PHY_REG(778, 21)
#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
#define HV_LATECOL_LOWER PHY_REG(778, 24)
#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
#define HV_COLC_LOWER PHY_REG(778, 26)
#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
#define HV_DC_LOWER PHY_REG(778, 28)
#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
#define HV_TNCRS_LOWER PHY_REG(778, 30)
#define HV_OEM_BITS PHY_REG(768, 25)
#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
#define HV_PM_CTRL PHY_REG(770, 17)
#define I2_DFT_CTRL PHY_REG(769, 20)
#define I2_SMBUS_CTRL PHY_REG(769, 23)
#define I217_INBAND_CTRL PHY_REG(770, 18)
#define I82579_LPI_CTRL PHY_REG(772, 20)