Symbol: PHASE
sys/arch/luna88k/stand/boot/sc.c
341
if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE)
sys/arch/luna88k/stand/boot/sc.c
343
hd->scsi_pctl = hs->sc_phase = hd->scsi_psns & PHASE;
sys/arch/luna88k/stand/boot/sc.c
545
hs->sc_phase = hd->scsi_psns & PHASE;
sys/arch/luna88k/stand/boot/sc.c
588
hs->sc_phase = hd->scsi_psns & PHASE;
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
55
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
56
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
57
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
58
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
60
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
61
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
62
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
63
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1203
clock_hz = REG_READ(PHASE[inst]);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1313
REG_WRITE(PHASE[inst], pixel_clk);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1343
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1347
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
989
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
993
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
105
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
106
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
107
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
108
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
120
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
121
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
122
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
123
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
135
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
136
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
137
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
138
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
139
SRII(PHASE, DP_DTO, 4),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
153
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
154
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
176
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
177
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
178
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
179
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
228
uint32_t PHASE[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
60
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
61
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
62
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
63
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
64
SRII(PHASE, DP_DTO, 4),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
65
SRII(PHASE, DP_DTO, 5),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
81
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
82
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
90
SRII(PHASE, DP_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
91
SRII(PHASE, DP_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
92
SRII(PHASE, DP_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
93
SRII(PHASE, DP_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1250
DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1251
DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
200
SRII_ARR_2(PHASE, DP_DTO, 0, index), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
201
SRII_ARR_2(PHASE, DP_DTO, 1, index), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
202
SRII_ARR_2(PHASE, DP_DTO, 2, index), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
203
SRII_ARR_2(PHASE, DP_DTO, 3, index), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
637
DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
638
DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \
usr.sbin/smtpd/parse.y
185
%token PHASE PKI PORT PROC PROC_EXEC PROTOCOLS PROXY_V2
usr.sbin/smtpd/parse.y
1965
FILTER STRING PHASE {
usr.sbin/smtpd/parse.y
2743
{ "phase", PHASE },