regress/lib/libcrypto/utf8/utf8test.c
100
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
101
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
107
ASSERT(ret == -3);
regress/lib/libcrypto/utf8/utf8test.c
108
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
113
ASSERT(ret == 2);
regress/lib/libcrypto/utf8/utf8test.c
114
ASSERT((value & 0x3F) == (j & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
115
ASSERT(value >> 6 == (i & 0x1F));
regress/lib/libcrypto/utf8/utf8test.c
133
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
134
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
141
ASSERT(ret == -3);
regress/lib/libcrypto/utf8/utf8test.c
142
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
148
ASSERT(ret == -4);
regress/lib/libcrypto/utf8/utf8test.c
149
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
155
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
156
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
160
ASSERT(ret == 3);
regress/lib/libcrypto/utf8/utf8test.c
161
ASSERT((value & 0x3F) == (k & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
162
ASSERT(((value >> 6) & 0x3F) == (j & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
163
ASSERT(value >> 12 == (i & 0x0F));
regress/lib/libcrypto/utf8/utf8test.c
185
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
186
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
194
ASSERT(ret == -3);
regress/lib/libcrypto/utf8/utf8test.c
195
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
201
ASSERT(ret == -4);
regress/lib/libcrypto/utf8/utf8test.c
202
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
208
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
209
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
213
ASSERT(ret == 4);
regress/lib/libcrypto/utf8/utf8test.c
214
ASSERT((value & 0x3F) == (l & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
215
ASSERT(((value >> 6) & 0x3F) ==
regress/lib/libcrypto/utf8/utf8test.c
217
ASSERT(((value >> 12) & 0x3F) ==
regress/lib/libcrypto/utf8/utf8test.c
219
ASSERT(value >> 18 == (i & 0x07));
regress/lib/libcrypto/utf8/utf8test.c
234
ASSERT(ret == 1);
regress/lib/libcrypto/utf8/utf8test.c
238
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
239
ASSERT(memcmp(testbuf, zerobuf, sizeof testbuf) == 0);
regress/lib/libcrypto/utf8/utf8test.c
242
ASSERT(ret == 1);
regress/lib/libcrypto/utf8/utf8test.c
243
ASSERT(testbuf[0] == i);
regress/lib/libcrypto/utf8/utf8test.c
244
ASSERT(memcmp(testbuf+1, zerobuf, sizeof(testbuf)-1) == 0);
regress/lib/libcrypto/utf8/utf8test.c
250
ASSERT(ret == 2);
regress/lib/libcrypto/utf8/utf8test.c
254
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
255
ASSERT(memcmp(testbuf, zerobuf, sizeof testbuf) == 0);
regress/lib/libcrypto/utf8/utf8test.c
258
ASSERT(ret == 2);
regress/lib/libcrypto/utf8/utf8test.c
259
ASSERT(memcmp(testbuf+2, zerobuf, sizeof(testbuf)-2) == 0);
regress/lib/libcrypto/utf8/utf8test.c
261
ASSERT(ret == 2);
regress/lib/libcrypto/utf8/utf8test.c
262
ASSERT(value == i);
regress/lib/libcrypto/utf8/utf8test.c
270
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
275
ASSERT(ret == 3);
regress/lib/libcrypto/utf8/utf8test.c
279
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
280
ASSERT(memcmp(testbuf, zerobuf, sizeof testbuf) == 0);
regress/lib/libcrypto/utf8/utf8test.c
283
ASSERT(ret == 3);
regress/lib/libcrypto/utf8/utf8test.c
284
ASSERT(memcmp(testbuf+3, zerobuf, sizeof(testbuf)-3) == 0);
regress/lib/libcrypto/utf8/utf8test.c
286
ASSERT(ret == 3);
regress/lib/libcrypto/utf8/utf8test.c
287
ASSERT(value == i);
regress/lib/libcrypto/utf8/utf8test.c
293
ASSERT(ret == 4);
regress/lib/libcrypto/utf8/utf8test.c
297
ASSERT(ret == -1);
regress/lib/libcrypto/utf8/utf8test.c
298
ASSERT(memcmp(testbuf, zerobuf, sizeof testbuf) == 0);
regress/lib/libcrypto/utf8/utf8test.c
301
ASSERT(ret == 4);
regress/lib/libcrypto/utf8/utf8test.c
302
ASSERT(memcmp(testbuf+4, zerobuf, sizeof(testbuf)-4) == 0);
regress/lib/libcrypto/utf8/utf8test.c
304
ASSERT(ret == 4);
regress/lib/libcrypto/utf8/utf8test.c
305
ASSERT(value == i);
regress/lib/libcrypto/utf8/utf8test.c
311
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
315
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
52
ASSERT(ret == 0);
regress/lib/libcrypto/utf8/utf8test.c
53
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
59
ASSERT(ret == 1);
regress/lib/libcrypto/utf8/utf8test.c
60
ASSERT(value == i);
regress/lib/libcrypto/utf8/utf8test.c
63
ASSERT(ret == 1);
regress/lib/libcrypto/utf8/utf8test.c
64
ASSERT(value == i);
regress/lib/libcrypto/utf8/utf8test.c
78
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
79
ASSERT(value == UNCHANGED);
regress/lib/libcrypto/utf8/utf8test.c
85
ASSERT(ret == -2);
regress/lib/libcrypto/utf8/utf8test.c
86
ASSERT(value == UNCHANGED);
regress/lib/libpthread/blocked_close/blocked_close.c
90
ASSERT(value_ptr == (void *)EBADF);
regress/lib/libpthread/blocked_dup2/blocked_dup2.c
94
ASSERT(value_ptr == (void *)EBADF);
regress/lib/libpthread/blocked_fifo/blocked_fifo.c
113
ASSERT(S_ISFIFO(st.st_mode));
regress/lib/libpthread/blocked_fifo/blocked_fifo.c
115
ASSERT(rlen == 4);
regress/lib/libpthread/blocked_fifo/blocked_fifo.c
135
ASSERT(fd == expected_fd);
regress/lib/libpthread/blocked_fifo/blocked_fifo.c
136
ASSERT(close(fd) == -1);
regress/lib/libpthread/blocked_fifo/blocked_fifo.c
137
ASSERT(errno == EBADF);
regress/lib/libpthread/blocked_join/blocked_join.c
25
ASSERT(pthread_join(mainthread, NULL) == EDEADLK);
regress/lib/libpthread/blocked_shutdown/blocked_shutdown.c
90
ASSERT(value_ptr == NULL);
regress/lib/libpthread/cancel/cancel.c
117
ASSERT(message_seen == 1);
regress/lib/libpthread/cancel/cancel.c
157
ASSERT(c4_cancel_early == 0);
regress/lib/libpthread/cancel/cancel.c
76
ASSERT(c2_in_test);
regress/lib/libpthread/cancel2/cancel2.c
106
ASSERT(result == PTHREAD_CANCELED);
regress/lib/libpthread/cancel2/cancel2.c
113
ASSERT(result == PTHREAD_CANCELED);
regress/lib/libpthread/cancel2/cancel2.c
92
ASSERT(result == PTHREAD_CANCELED);
regress/lib/libpthread/cancel2/cancel2.c
99
ASSERT(result == PTHREAD_CANCELED);
regress/lib/libpthread/cancel_wait/cancel_wait.c
104
ASSERT(ret == NULL);
regress/lib/libpthread/cancel_wait/cancel_wait.c
105
ASSERT(WIFSIGNALED(status));
regress/lib/libpthread/cancel_wait/cancel_wait.c
106
ASSERT(WTERMSIG(status) == 9);
regress/lib/libpthread/cancel_wait/cancel_wait.c
72
ASSERT(ret == PTHREAD_CANCELED);
regress/lib/libpthread/cancel_wait/cancel_wait.c
73
ASSERT(status == 42);
regress/lib/libpthread/cancel_wait/cancel_wait.c
80
ASSERT(ret == PTHREAD_CANCELED);
regress/lib/libpthread/cancel_wait/cancel_wait.c
81
ASSERT(status == 42);
regress/lib/libpthread/cancel_wait/cancel_wait.c
88
ASSERT(ret == PTHREAD_CANCELED);
regress/lib/libpthread/cancel_wait/cancel_wait.c
89
ASSERT(status == 42);
regress/lib/libpthread/cancel_wait/cancel_wait.c
96
ASSERT(ret == PTHREAD_CANCELED);
regress/lib/libpthread/cancel_wait/cancel_wait.c
97
ASSERT(status == 42);
regress/lib/libpthread/close/close.c
110
ASSERT((ret = select(fd + 1, &r, NULL, NULL, NULL)) == -1);
regress/lib/libpthread/close/close.c
111
ASSERT(errno == EBADF);
regress/lib/libpthread/close_race/close_race.c
74
ASSERT(value_ptr == (void *)EBADF);
regress/lib/libpthread/closefrom/closefrom.c
38
ASSERT(result == -1 && errno == EBADF);
regress/lib/libpthread/cwd/cwd.c
51
ASSERT(path = getcwd(wd, sizeof wd));
regress/lib/libpthread/cwd/cwd.c
53
ASSERT(path = getwd(wd));
regress/lib/libpthread/dup2_race/dup2_race.c
76
ASSERT(value_ptr == (void *)EBADF);
regress/lib/libpthread/errno/errno.c
101
ASSERT(&errno == t1_errno);
regress/lib/libpthread/errno/errno.c
104
ASSERT(&errno == t1_errno);
regress/lib/libpthread/errno/errno.c
105
ASSERT(pthread_equal(t1_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
129
ASSERT(*main_errno == 0);
regress/lib/libpthread/errno/errno.c
130
ASSERT(errno == 0);
regress/lib/libpthread/errno/errno.c
142
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
147
ASSERT(r == -1);
regress/lib/libpthread/errno/errno.c
152
ASSERT(r == -1);
regress/lib/libpthread/errno/errno.c
160
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
164
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
165
ASSERT(pthread_equal(main_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
169
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
173
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
174
ASSERT(pthread_equal(main_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
178
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
182
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
183
ASSERT(pthread_equal(main_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
188
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
189
ASSERT(pthread_equal(main_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
37
ASSERT(state == new_state - 1);
regress/lib/libpthread/errno/errno.c
60
ASSERT(signal == SIGUSR1);
regress/lib/libpthread/errno/errno.c
63
ASSERT(&errno == main_errno);
regress/lib/libpthread/errno/errno.c
65
ASSERT(pthread_equal(t1_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
68
ASSERT(&errno == t1_errno);
regress/lib/libpthread/errno/errno.c
70
ASSERT(pthread_equal(t1_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
74
ASSERT(&errno == t2_errno);
regress/lib/libpthread/errno/errno.c
76
ASSERT(pthread_equal(t2_tid, pthread_self()));
regress/lib/libpthread/errno/errno.c
86
ASSERT(t1_errno != main_errno);
regress/lib/libpthread/errno/errno.c
87
ASSERT(*t1_errno == 0);
regress/lib/libpthread/errno/errno.c
95
ASSERT(pthread_equal(main_tid, t1_tid) == 0);
regress/lib/libpthread/errno/errno.c
96
ASSERT(&errno == t1_errno);
regress/lib/libpthread/fork/fork.c
101
ASSERT(getpid() == parent_pid);
regress/lib/libpthread/fork/fork.c
105
ASSERT(WIFEXITED(status));
regress/lib/libpthread/fork/fork.c
106
ASSERT(WEXITSTATUS(status) == 0);
regress/lib/libpthread/fork/fork.c
89
ASSERT(getpid() != parent_pid);
regress/lib/libpthread/group/group.c
56
ASSERT(grp->gr_name != fail);
regress/lib/libpthread/group/group.c
59
ASSERT(grp->gr_gid == gid);
regress/lib/libpthread/malloc_duel/malloc_duel.c
37
ASSERT(a != NULL);
regress/lib/libpthread/malloc_duel/malloc_duel.c
41
ASSERT(a[i] != NULL);
regress/lib/libpthread/malloc_duel/malloc_duel.c
68
ASSERT(signal(SIGALRM, alarm_handler) != SIG_ERR);
regress/lib/libpthread/pause/pause.c
65
ASSERT(signal(SIGHUP, handler) != SIG_ERR);
regress/lib/libpthread/pcap/pcap.c
41
ASSERT(ioctl(pcap_fileno(handle), BIOCIMMEDIATE, &on) != -1);
regress/lib/libpthread/pcap/pcap.c
44
ASSERT(pcap_loop(handle, PKTCNT, packet_ignore, 0) != -1);
regress/lib/libpthread/pcap/pcap.c
53
ASSERT(system("ping -c 3 127.0.0.1") == 0);
regress/lib/libpthread/pcap/pcap.c
73
ASSERT(packet_count == 3);
regress/lib/libpthread/poll/poll.c
117
ASSERT(p[0].revents == 0);
regress/lib/libpthread/poll/poll.c
118
ASSERT(p[1].revents == POLLOUT);
regress/lib/libpthread/poll/poll.c
128
ASSERT(p[0].revents == POLLIN);
regress/lib/libpthread/poll/poll.c
80
ASSERT((p[0].revents & POLLIN) == POLLIN);
regress/lib/libpthread/poll/poll.c
81
ASSERT((p[1].revents & POLLOUT) == POLLOUT);
regress/lib/libpthread/poll/poll.c
97
ASSERT((p[0].revents & POLLNVAL) == POLLNVAL);
regress/lib/libpthread/poll/poll.c
98
ASSERT((p[1].revents & POLLOUT) == POLLOUT);
regress/lib/libpthread/preemption_float/preemption_float.c
126
ASSERT(*result == 0);
regress/lib/libpthread/preemption_float/preemption_float.c
133
ASSERT(*result == 0);
regress/lib/libpthread/preemption_float/preemption_float.c
138
ASSERT(floatloop() == 0);
regress/lib/libpthread/process_kill/process_kill.c
37
ASSERT(signal(SIGALRM, deadlock) != SIG_ERR);
regress/lib/libpthread/process_kill/process_kill.c
38
ASSERT(signal(SIGUSR1, handler) != SIG_ERR);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
114
ASSERT(cnt == 1);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
117
ASSERT(cnt == 0);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
18
ASSERT(cnt == 1);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
25
ASSERT(cnt == 2);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
32
ASSERT(cnt == 0);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
39
ASSERT(cnt == 2);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
46
ASSERT(cnt == 0);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
53
ASSERT(cnt == 3);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
69
ASSERT(cnt == 3);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
73
ASSERT(cnt == 2);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
94
ASSERT(cnt == 4);
regress/lib/libpthread/pthread_atfork/pthread_atfork.c
98
ASSERT(cnt == 0);
regress/lib/libpthread/pthread_kill/pthread_kill.c
24
ASSERT(sa.sa_handler == SIG_DFL);
regress/lib/libpthread/pthread_kill/pthread_kill.c
25
ASSERT(siginfo != NULL);
regress/lib/libpthread/pthread_kill/pthread_kill.c
48
ASSERT(errno == EINTR);
regress/lib/libpthread/pthread_mutex/pthread_mutex.c
63
ASSERT(contention_variable == 1);
regress/lib/libpthread/pthread_mutex/pthread_mutex.c
83
ASSERT(contention_variable == 2);
regress/lib/libpthread/pthread_once/pthread_once.c
42
ASSERT(!done);
regress/lib/libpthread/pthread_once/pthread_once.c
46
ASSERT(done);
regress/lib/libpthread/pthread_specific/pthread_specific.c
55
ASSERT(p == pthread_self());
regress/lib/libpthread/pthread_specific/pthread_specific.c
91
ASSERT(destroy_run > 0);
regress/lib/libpthread/pw/pw.c
58
ASSERT(pwbuf.pw_uid == getuid());
regress/lib/libpthread/readdir/readdir.c
63
ASSERT(found);
regress/lib/libpthread/restart/accept/accept.c
35
ASSERT(accept(s, (struct sockaddr *)&sa, &salen) == -1);
regress/lib/libpthread/restart/accept/accept.c
65
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/accept/accept.c
66
ASSERT(hits == 2);
regress/lib/libpthread/restart/connect/connect.c
39
ASSERT(connect(s, (struct sockaddr *)&sa, sizeof(sa)) == -1);
regress/lib/libpthread/restart/connect/connect.c
41
ASSERT(connect(s, (struct sockaddr *)&sa, sizeof(sa)) == -1);
regress/lib/libpthread/restart/connect/connect.c
42
ASSERT(errno == EALREADY);
regress/lib/libpthread/restart/connect/connect.c
66
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/connect/connect.c
67
ASSERT(hits == 1);
regress/lib/libpthread/restart/kevent/kevent.c
29
ASSERT(kevent(kq, NULL, 0, &ev, 1, &ts) == -1);
regress/lib/libpthread/restart/kevent/kevent.c
53
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/kevent/kevent.c
54
ASSERT(hits == 1);
regress/lib/libpthread/restart/read/read.c
26
ASSERT(read(fds[0], &buf, 1) == -1);
regress/lib/libpthread/restart/read/read.c
56
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/read/read.c
57
ASSERT(hits == 2);
regress/lib/libpthread/restart/readv/readv.c
30
ASSERT(readv(fds[0], &iov, 1) == -1);
regress/lib/libpthread/restart/readv/readv.c
60
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/readv/readv.c
61
ASSERT(hits == 2);
regress/lib/libpthread/restart/recvfrom/recvfrom.c
35
ASSERT(recvfrom(s, &buf, 1, 0,(struct sockaddr *)&sa, &salen) == -1);
regress/lib/libpthread/restart/recvfrom/recvfrom.c
65
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/recvfrom/recvfrom.c
66
ASSERT(hits == 2);
regress/lib/libpthread/restart/recvmsg/recvmsg.c
41
ASSERT(recvmsg(s, &msg, 0) == -1);
regress/lib/libpthread/restart/recvmsg/recvmsg.c
71
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/restart/recvmsg/recvmsg.c
72
ASSERT(hits == 2);
regress/lib/libpthread/semaphore/sem_destroy/sem_destroy.c
26
ASSERT(errno == EINVAL);
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
19
ASSERT(val == 0);
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
23
ASSERT(val == 1);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
103
ASSERT(timespeccmp(&ts2, &ts, <=));
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
123
ASSERT(value == 0);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
124
ASSERT(posted != 0);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
126
ASSERT(r == -1);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
127
ASSERT(errno == EINTR);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
128
ASSERT(eintr_ok);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
130
ASSERT(value == 1);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
132
ASSERT(value == 0);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
44
ASSERT(errno == EINVAL);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
54
ASSERT(errno == EBUSY);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
83
ASSERT(errno == ETIMEDOUT);
regress/lib/libpthread/semaphore/sem_timedwait/sem_timedwait.c
90
ASSERT(timespeccmp(&ts, &ts2, <=));
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
19
ASSERT(errno == EINVAL);
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
24
ASSERT(errno == EAGAIN);
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
30
ASSERT(val == 0);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
35
ASSERT(errno == EINVAL);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
45
ASSERT(errno == EBUSY);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
86
ASSERT(value == 0);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
87
ASSERT(posted != 0);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
89
ASSERT(r == -1);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
90
ASSERT(errno == EINTR);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
91
ASSERT(eintr_ok);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
93
ASSERT(value == 1);
regress/lib/libpthread/semaphore/sem_wait/sem_wait.c
95
ASSERT(value == 0);
regress/lib/libpthread/setjmp/setjmp.c
48
ASSERT(reached);
regress/lib/libpthread/setjmp/setjmp.c
63
ASSERT(reached);
regress/lib/libpthread/setsockopt/1/setsockopt1.c
33
ASSERT(signal(SIGALRM, alarm_handler) != SIG_ERR);
regress/lib/libpthread/setsockopt/1/setsockopt1.c
36
ASSERT(read(s, &buf, sizeof(buf)) == -1);
regress/lib/libpthread/setsockopt/1/setsockopt1.c
38
ASSERT(errno == EAGAIN);
regress/lib/libpthread/setsockopt/1/setsockopt1.c
45
ASSERT(timespeccmp(&e, to, >));
regress/lib/libpthread/setsockopt/1/setsockopt1.c
47
ASSERT(timespeccmp(&t1, &mono_res_times2, <=));
regress/lib/libpthread/setsockopt/2/setsockopt2.c
101
ASSERT(WIFEXITED(status));
regress/lib/libpthread/setsockopt/2/setsockopt2.c
34
ASSERT(signal(SIGALRM, alarm_handler) != SIG_ERR);
regress/lib/libpthread/setsockopt/2/setsockopt2.c
37
ASSERT(read(s, &buf, sizeof(buf)) == -1);
regress/lib/libpthread/setsockopt/2/setsockopt2.c
39
ASSERT(errno == EAGAIN);
regress/lib/libpthread/setsockopt/2/setsockopt2.c
50
ASSERT(timespeccmp(&t1, &mono_res, <=));
regress/lib/libpthread/setsockopt/3/setsockopt3.c
41
ASSERT(WIFEXITED(status));
regress/lib/libpthread/setsockopt/3/setsockopt3.c
42
ASSERT(WEXITSTATUS(status) == 0);
regress/lib/libpthread/setsockopt/3a/setsockopt3a.c
33
ASSERT(signal(SIGALRM, alarm_handler) != SIG_ERR);
regress/lib/libpthread/setsockopt/3a/setsockopt3a.c
36
ASSERT(read(s, &buf, sizeof(buf)) == -1);
regress/lib/libpthread/setsockopt/3a/setsockopt3a.c
38
ASSERT(errno == EAGAIN);
regress/lib/libpthread/setsockopt/3a/setsockopt3a.c
49
ASSERT(timespeccmp(&t1, &mono_res, <=));
regress/lib/libpthread/sigdeliver/sigdeliver.c
36
ASSERT(signal(SIGUSR1, sighandler) != SIG_ERR);
regress/lib/libpthread/sigdeliver/sigdeliver.c
38
ASSERT(got_signal != 0);
regress/lib/libpthread/siginfo/siginfo.c
24
ASSERT(sa.sa_handler == SIG_DFL);
regress/lib/libpthread/siginfo/siginfo.c
25
ASSERT(siginfo != NULL);
regress/lib/libpthread/siginfo/siginfo.c
30
ASSERT(siginfo->si_addr == BOGUS);
regress/lib/libpthread/siginfo/siginfo.c
31
ASSERT(siginfo->si_code == SEGV_MAPERR ||
regress/lib/libpthread/siginterrupt/siginterrupt.c
25
ASSERT(read(fds[0], &buf, 1) == -1);
regress/lib/libpthread/siginterrupt/siginterrupt.c
35
ASSERT(signal(SIGUSR1, handler) != SIG_ERR);
regress/lib/libpthread/siginterrupt/siginterrupt.c
55
ASSERT(retval == (void *)EINTR);
regress/lib/libpthread/siginterrupt/siginterrupt.c
56
ASSERT(hits == 3);
regress/lib/libpthread/sigmask/sigmask.c
47
ASSERT(sig == SIGALRM);
regress/lib/libpthread/signal/signal.c
25
ASSERT(sleep(3) == 0);
regress/lib/libpthread/signal/signal.c
46
ASSERT(signal(SIGALRM, handler) != SIG_ERR);
regress/lib/libpthread/signals/ignore_sigchild/ignore_sigchild.c
17
ASSERT(signal(SIGCHLD, SIG_IGN) != SIG_ERR);
regress/lib/libpthread/signals/ignore_sigchild/ignore_sigchild.c
30
ASSERT(wait(&status) == -1);
regress/lib/libpthread/signals/ignore_sigchild/ignore_sigchild.c
31
ASSERT(errno == ECHILD);
regress/lib/libpthread/signals/pthread_join/pthread_join.c
52
ASSERT(hits == 1);
regress/lib/libpthread/signals/pthread_join/pthread_join.c
54
ASSERT(retval == (void *)0);
regress/lib/libpthread/signals/pthread_mutex_lock/pthread_mutex_lock.c
44
ASSERT(hits == 1);
regress/lib/libpthread/signodefer/signodefer.c
28
ASSERT(siginfo != NULL);
regress/lib/libpthread/signodefer/signodefer.c
50
ASSERT(sigaction(SIGUSR1, &act, NULL) == 0);
regress/lib/libpthread/signodefer/signodefer.c
55
ASSERT(was_active == 0);
regress/lib/libpthread/signodefer/signodefer.c
59
ASSERT(sigaction(SIGUSR1, &act, NULL) == 0);
regress/lib/libpthread/signodefer/signodefer.c
64
ASSERT(was_active == 1);
regress/lib/libpthread/sigsuspend/sigsuspend.c
128
ASSERT(set == tmp);
regress/lib/libpthread/sigsuspend/sigsuspend.c
206
ASSERT(sigcounts[SIGIO] == 0);
regress/lib/libpthread/sigsuspend/sigsuspend.c
218
ASSERT(sigcounts[SIGURG] == 2);
regress/lib/libpthread/sigsuspend/sigsuspend.c
229
ASSERT(sigcounts[SIGUSR2] == 2);
regress/lib/libpthread/sigsuspend/sigsuspend.c
241
ASSERT(sigcounts[SIGUSR1] == 0);
regress/lib/libpthread/sigwait/sigwait.c
168
ASSERT(sigcounts[SIGIO] == 0);
regress/lib/libpthread/sigwait/sigwait.c
180
ASSERT(sigcounts[SIGURG] == 2);
regress/lib/libpthread/sigwait/sigwait.c
212
ASSERT(sigcounts[SIGHUP] == 2);
regress/lib/libpthread/sigwait/sigwait.c
230
ASSERT(sigcounts[SIGHUP] == 1);
regress/lib/libpthread/sigwait/sigwait.c
244
ASSERT(sigcounts[SIGUSR1] == 1);
regress/lib/libpthread/sigwait/sigwait.c
251
ASSERT(sigcounts[SIGUSR1] == 2);
regress/lib/libpthread/socket/1/socket1.c
141
ASSERT(++counter == 1);
regress/lib/libpthread/socket/1/socket1.c
151
ASSERT(++counter == 4);
regress/lib/libpthread/socket/1/socket1.c
162
ASSERT(++counter == atoi(buf));
regress/lib/libpthread/socket/1/socket1.c
191
ASSERT(success == 2);
regress/lib/libpthread/socket/1/socket1.c
75
ASSERT(++counter == 2);
regress/lib/libpthread/socket/1/socket1.c
82
ASSERT(++counter == 3);
regress/lib/libpthread/socket/1/socket1.c
95
ASSERT(++counter == atoi(buf));
regress/lib/libpthread/socket/2/socket2.c
84
ASSERT(WIFEXITED(status));
regress/lib/libpthread/socket/2/socket2.c
85
ASSERT(WEXITSTATUS(status) == 0);
regress/lib/libpthread/socket/3/socket3.c
106
ASSERT(flags & O_NONBLOCK);
regress/lib/libpthread/stack/stack.c
114
ASSERT(addr == addr2);
regress/lib/libpthread/stack/stack.c
124
ASSERT(size == size2);
regress/lib/libpthread/stack/stack.c
136
ASSERT(mquery(addr, pagesize, PROT_READ, MAP_FIXED|MAP_ANON, -1, 0)
regress/lib/libpthread/stack/stack.c
142
ASSERT(size == size2);
regress/lib/libpthread/stack/stack.c
149
ASSERT(addr != MAP_FAILED);
regress/lib/libpthread/stack/stack.c
154
ASSERT(size2 == size);
regress/lib/libpthread/stack/stack.c
156
ASSERT(addr2 == addr);
regress/lib/libpthread/stack/stack.c
158
ASSERT(addr2 == addr);
regress/lib/libpthread/stack/stack.c
159
ASSERT(size2 == size);
regress/lib/libpthread/stack/stack.c
52
ASSERT((char *)&s >= s->addr && (char *)&s - s->addr < s->size);
regress/lib/libpthread/stack/stack.c
73
ASSERT(size != 1); /* must have changed */
regress/lib/libpthread/stack/stack.c
74
ASSERT(size != 0); /* we default to having a guardpage */
regress/lib/libpthread/stack/stack.c
78
ASSERT(size >= PTHREAD_STACK_MIN);
regress/lib/libpthread/stack/stack.c
82
ASSERT(addr == NULL); /* default must be NULL */
regress/lib/libpthread/stack/stack.c
87
ASSERT(addr2 == addr); /* must match the other calls */
regress/lib/libpthread/stack/stack.c
88
ASSERT(size2 == size);
regress/lib/libpthread/stack/stack.c
92
ASSERT(err == EINVAL);
regress/lib/libpthread/stack/stack.c
94
ASSERT(size2 == size);
regress/lib/libpthread/stdarg/stdarg.c
53
ASSERT(0);
regress/lib/libpthread/stdarg/stdarg.c
69
ASSERT(test1("iclp", 1234, 'x', 123456789L, &thing) == 9);
regress/lib/libpthread/stdio/stdio.c
63
ASSERT(ftell(fp) == statbuf.st_size);
regress/lib/libpthread/stdio/stdio.c
80
ASSERT(fp1 == fp2);
regress/lib/libpthread/stdio/stdio.c
92
ASSERT(sscanf(str, "%d %lf", &i, &d) == 2);
regress/lib/libpthread/stdio/stdio.c
96
ASSERT(strcmp(buf, str) == 0);
regress/lib/libpthread/switch/switch.c
114
ASSERT(x[i]); /* make sure each thread ran */
regress/lib/libpthread/system/system.c
17
ASSERT(system("ls") == 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13192
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
807
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
815
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8788
ASSERT(link->link_enc);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1075
ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1160
ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
491
ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
532
ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
207
ASSERT(i != copy_of_link_table.stream_count);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1268
ASSERT(0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
647
ASSERT(gb_addr_config != 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/dc_fpu.c
66
ASSERT(depth >= 1);
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
118
ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
159
ASSERT(res.value <= BW_FIXED_MAX_I32);
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
165
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
171
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
180
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
53
ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
70
ASSERT(denominator != 0);
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
76
ASSERT(res_value <= BW_FIXED_MAX_I32);
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
98
ASSERT(res_value <= MAX_I64 - summand);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2806
ASSERT(pipe[i].plane_state);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
108
ASSERT(res_value <= LLONG_MAX - summand);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
145
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
151
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
160
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
188
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
192
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
201
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
311
ASSERT(dc_fixpt_lt(arg, dc_fixpt_one));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
353
ASSERT(m != 0);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
355
ASSERT(dc_fixpt_lt(
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
380
ASSERT(arg.value > 0);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
86
ASSERT(res_value <= LONG_MAX);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1100
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
2005
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3776
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c
165
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
379
ASSERT(0); /* Unknown Asic */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
139
ASSERT(dprefclk_src_sel == 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
146
ASSERT(pipe_ctx != NULL);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
88
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
202
ASSERT(clk_mgr->pp_smu);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
119
ASSERT(result == VBIOSSMC_Result_OK);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
493
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
623
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
636
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
660
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
126
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
162
ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz));
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
214
ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
125
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
425
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
555
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
584
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
594
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
709
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
722
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
461
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
552
ASSERT(clock);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
580
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
592
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
705
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
718
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
134
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
140
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
657
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
768
ASSERT(is_valid_clock_value(max_fclk));
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
777
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
837
ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
867
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
947
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
960
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
153
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
159
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
421
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
564
ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
565
ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
566
ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
567
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
635
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
648
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
170
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
387
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
478
ASSERT(clock);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
507
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
519
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
610
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
623
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
145
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
336
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1056
ASSERT(clock_table->NumMemPstatesEnabled &&
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1069
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1073
ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1136
ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1174
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1406
ASSERT(clk_mgr->smu_wm_set.wm_set);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1417
ASSERT(smu_dpm_clks.dpm_clks);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
304
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
905
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
143
ASSERT(result == VBIOSSMC_Result_OK);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
168
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
175
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
537
ASSERT(otg_master);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
538
ASSERT(otg_master->clock_source);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
539
ASSERT(otg_master->clock_source->funcs->program_pix_clk);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
540
ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
578
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2534
ASSERT(dc->dcn_ip->max_num_dpp);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3326
ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3468
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4120
ASSERT(top_pipe_to_program != NULL);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4314
ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5222
ASSERT(update_type < UPDATE_TYPE_FULL);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5253
ASSERT(update_type >= UPDATE_TYPE_FULL);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5472
ASSERT(dc->current_state->stream_count == 0);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5887
ASSERT(payload->length <= 16);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5954
ASSERT(link_index != 0xFF);
sys/dev/pci/drm/amd/display/dc/core/dc.c
6149
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc.c
6200
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1008
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1208
ASSERT(!pipe->plane_state->status.is_flip_pending);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
153
ASSERT(i != state->stream_count);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
296
ASSERT(state->stream_count == stream_count);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
297
ASSERT(dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
304
ASSERT(state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid == false);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
371
ASSERT(stream->link->is_dig_mapping_flexible != true);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
715
ASSERT(is_valid);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1345
ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1459
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1591
ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1980
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1984
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1999
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2003
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2054
ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE));
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2064
ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2403
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2465
ASSERT(resource_is_pipe_type(opp_head, OPP_HEAD));
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2474
ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2631
ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2726
ASSERT(res_ctx->dio_link_enc_ref_cnts[enc_index] > 0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2858
ASSERT(resource_get_odm_slice_count(otg_master) == 1);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2859
ASSERT(otg_master->plane_state == NULL);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2860
ASSERT(otg_master->stream_res.stream_enc);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2929
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2983
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2999
ASSERT(sec_pipe);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3008
ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3124
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3201
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3263
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3323
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3389
ASSERT(dpp_pipe_count > 0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3613
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4010
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4019
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5476
ASSERT(sec_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
913
ASSERT(mpc_slice_count == 1 ||
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
929
ASSERT(mpc_rec.height % 2 == 0);
sys/dev/pci/drm/amd/display/dc/core/dc_stat.c
59
ASSERT(status == DMUB_STATUS_OK);
sys/dev/pci/drm/amd/display/dc/core/dc_stat.c
89
ASSERT(status == DMUB_STATUS_OK);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
517
ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc_surface.c
122
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1440
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1471
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1590
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dc_helper.c
100
ASSERT(mask != 0);
sys/dev/pci/drm/amd/display/dc/dc_helper.c
449
ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
sys/dev/pci/drm/amd/display/dc/dc_helper.c
496
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dc_helper.c
638
ASSERT(!offload->gather_in_progress);
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
60
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
67
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1165
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2164
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
90
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
261
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
319
ASSERT(av_stream_map_lane_count != 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
340
ASSERT(audio_sdp_overhead != 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
158
ASSERT(dprefclk_src_sel == 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
516
ASSERT(pipe_ctx != NULL);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
594
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
595
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
402
ASSERT(arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
344
ASSERT(speed);
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
224
ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
240
ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
305
ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
451
ASSERT(cp2520_pattern == 2);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
503
ASSERT(cp2520_pattern == 2);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
989
ASSERT(result == BP_RESULT_OK);
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
713
ASSERT(pixels_per_frame);
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
714
ASSERT(pixels_per_second);
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
722
ASSERT(refresh_rate);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1241
ASSERT(audio_info);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
669
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
670
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
693
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
78
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
802
ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
862
ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
911
ASSERT(pixel_width);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
940
ASSERT(pixels_per_entries);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
126
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
223
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
39
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
90
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1123
ASSERT(timing != NULL);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c
73
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
215
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
226
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
128
ASSERT(audio_info);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c
61
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c
82
ASSERT(audio_info);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
189
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
383
ASSERT(cp2520_pattern == 2);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
860
ASSERT(result == BP_RESULT_OK);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1233
ASSERT(audio_info);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
620
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
621
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
71
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
225
ASSERT(info_packet->hb1 == DC_DP_INFOFRAME_TYPE_PPS);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
306
ASSERT(dsc_packed_pps);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
568
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
569
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
699
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
714
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
723
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
745
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
766
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
823
ASSERT (enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
139
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
140
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
264
ASSERT(enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
222
ASSERT(enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
97
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
98
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
210
ASSERT(enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
374
ASSERT(stream_enc_inst < 5 && link_enc_inst < 5);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
85
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
86
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
221
ASSERT(enc->afmt);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
574
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
97
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
98
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
sys/dev/pci/drm/amd/display/dc/dm_services.h
108
ASSERT(mask != 0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c
73
ASSERT(significance != 0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c
89
ASSERT(significance != 0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1262
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1321
ASSERT(fclks->num_levels);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
296
ASSERT(0); /* Not supported */
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
360
ASSERT(0); /* Not supported */
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
543
ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
977
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
979
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
982
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
984
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
147
ASSERT(dc->dcn_soc->number_of_channels < 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1309
ASSERT(0); /* Not supported */
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2095
ASSERT(context != dc->current_state);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2123
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2214
ASSERT(vlevel < dml->soc.num_states);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2247
ASSERT(bw_params);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2336
ASSERT(context != dc->current_state);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2415
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1249
ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1309
ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1115
ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1116
ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1118
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1304
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1305
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1336
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1337
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1379
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1392
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1398
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1405
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1424
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1439
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1475
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1476
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1482
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1483
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1509
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1523
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1598
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1633
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1663
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
610
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
918
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
927
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
937
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1116
ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1117
ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1119
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1305
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1306
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1337
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1338
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1380
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1393
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1399
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1406
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1425
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1440
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1476
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1477
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1483
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1484
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1510
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1524
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1599
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1634
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1664
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
610
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
918
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
927
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
938
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1633
ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1167
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1168
ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1170
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1368
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1369
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1404
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1405
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1449
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1471
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1481
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1491
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1527
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1543
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1583
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1584
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1590
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1591
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1617
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1620
ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1631
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1712
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1747
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1783
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
611
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
964
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
973
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
983
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
645
ASSERT(dummy_latency_index != max_latency_table_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1918
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2643
ASSERT(v->PrefetchModeSupported);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1037
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1054
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1218
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1273
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1274
ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1276
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1477
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1478
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1509
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1510
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1551
ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1553
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1571
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1577
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1584
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1621
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1636
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1674
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1675
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1681
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1682
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1708
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1711
ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1722
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
583
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
816
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
851
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
881
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
301
ASSERT(vlevel < dml->soc.num_states);
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
340
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
437
ASSERT(bw_params);
sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
313
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
319
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
607
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
683
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
746
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2116
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2917
ASSERT(v->PrefetchAndImmediateFlipSupported);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1089
} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1116
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1118
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1318
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1355
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1362
ASSERT(src->num_cursors <= 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1401
ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1403
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1419
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1423
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1427
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1458
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1471
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1474
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1500
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1504
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1523
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1526
ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1537
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
582
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
795
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
826
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
841
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
973
dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
985
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
204
ASSERT(dcn3_14_soc.num_chans);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
205
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
385
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2134
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2935
ASSERT(v->PrefetchAndImmediateFlipSupported);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1058
dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1072
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1177
} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1204
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1206
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1406
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1443
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1450
ASSERT(src->num_cursors <= 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1489
ASSERT(disp_dlg_regs->dst_y_after_scaler < 8);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1491
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1507
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1511
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1515
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1546
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1559
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1562
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1588
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1592
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1611
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1614
ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1625
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
670
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
882
ASSERT(cur_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
912
ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
926
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1683
ASSERT(usr_retraining_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1692
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1896
ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1910
ASSERT(sec_pipe->top_pipe == NULL);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1918
ASSERT(sec_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1924
ASSERT(pri_pipe->bottom_pipe != sec_pipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1931
ASSERT(pri_pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2028
ASSERT(0); /* Should never try to merge master pipe */
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2063
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2086
ASSERT(pipe_4to1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2105
ASSERT(pipe_4to1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2155
ASSERT(pipes);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2232
ASSERT(mpo_pipe->plane_state != pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
308
ASSERT(dummy_latency_index != max_latency_table_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3262
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
135
ASSERT(pte_row_height_linear >= 8);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
143
ASSERT(p1_pte_row_height_linear >= 8);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
272
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
344
ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
370
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
371
ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
372
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
426
ASSERT(src->num_cursors <= 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
441
ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
554
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
555
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
556
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
557
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
570
ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
571
ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
572
ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
580
ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
581
ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
589
ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
591
ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
600
ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
601
ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
602
ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
603
ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
604
ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
605
ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
606
ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
607
ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
608
ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
812
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
244
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
522
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
278
ASSERT(clk_table->num_entries);
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
555
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1104
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1114
ASSERT(total_pipes <= DC__NUM_DPP__MAX);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
261
ASSERT(plane_idx < DC__NUM_DPP__MAX);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
269
ASSERT(pipe_idx >= 0);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
873
ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
929
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1151
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1158
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1176
ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1346
ASSERT(dst_y_prefetch >= 2.0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1440
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1489
ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1490
ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1492
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1517
ASSERT(vratio_pre_l <= 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1523
ASSERT(vratio_pre_c <= 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1532
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1537
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1542
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1560
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1564
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1568
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1689
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1690
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1728
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1729
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1775
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1776
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1812
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1813
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1826
ASSERT(cur0_src_width <= 256);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
183
ASSERT(prefill > 0.0 && prefill <= 8.0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1861
ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1896
ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1904
ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1907
ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1918
ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
507
ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
526
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
831
ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
852
ASSERT(log2_dpte_row_height_linear >= 3);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
947
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
955
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10044
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10168
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10171
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1796
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2651
ASSERT(*PixelPTEReqWidth);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9389
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9700
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
103
ASSERT(significance != 0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
71
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
768
ASSERT(plane_idx < __DML_NUM_PLANES__);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
777
ASSERT(pipe_found != 0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
96
ASSERT(significance != 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
307
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
492
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
688
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
753
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
777
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
189
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
410
ASSERT(dml_stream_idx >= 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
466
ASSERT(phantom_status);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
493
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
354
ASSERT(dc_main_pipes[dc_pipe_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
371
ASSERT(dc_phantom_pipes[dc_pipe_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
394
ASSERT(dc_main_pipes[dc_pipe_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
408
ASSERT(dc_phantom_pipes[dc_pipe_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c
49
ASSERT(significance != 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_debug.h
9
#define DML_ASSERT(condition) ASSERT(condition)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
104
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1091
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1106
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1139
ASSERT(scratch.odm_info.odm_factor * scratch.mpc_info.mpc_factor > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1148
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1155
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1162
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
401
ASSERT(pipes_needed <= 0); // Validation should prevent us from building a pipe context that exceeds the number of HW resoruces available
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
467
ASSERT(pipes_needed == 0); // Validation should prevent us from building a pipe context that exceeds the number of HW resoruces available
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
521
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
543
ASSERT(scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine == 1 || scratch->pipe_pool.num_pipes_assigned_to_plane_for_odm_combine == 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
619
ASSERT(master_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
625
ASSERT(pipes_assigned == pipes_needed);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
655
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
662
ASSERT(master_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
668
ASSERT(pipes_assigned >= pipes_needed);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
763
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
816
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
822
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
838
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
891
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
91
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
915
ASSERT(dpp_pipe_count > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1178
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1331
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1371
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
999
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
162
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
315
ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
316
ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
183
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
207
ASSERT(dml_result);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
291
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
373
ASSERT(min_state_for_g6_temp_read >= 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
457
ASSERT(need_recalculation == false);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
133
ASSERT(pte_row_height_linear >= 8);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
140
ASSERT(p1_pte_row_height_linear >= 8);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
282
ASSERT(refclk_freq_in_mhz != 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
283
ASSERT(pclk_freq_in_mhz != 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
284
ASSERT(ref_freq_to_pix_freq < 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
315
ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
358
ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
359
ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
360
ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
401
ASSERT(num_cursors <= 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
412
ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
504
ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
505
ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
506
ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
507
ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
521
ASSERT(disp_dlg_regs->dst_y_after_scaler < (dml_uint_t)8);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
522
ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
523
ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (dml_uint_t)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
529
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (dml_uint_t)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
530
ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (dml_uint_t)dml_pow(2, 17));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
538
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
540
ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
549
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
550
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_c < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
551
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
552
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
553
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
554
ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (dml_uint_t)dml_pow(2, 13));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
555
ASSERT(disp_ttu_regs->qos_level_low_wm < (dml_uint_t) dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
556
ASSERT(disp_ttu_regs->qos_level_high_wm < (dml_uint_t) dml_pow(2, 14));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
557
ASSERT(disp_ttu_regs->min_ttu_vblank < (dml_uint_t) dml_pow(2, 24));
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
100
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
503
ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
535
ASSERT(0); // LUT select was updated again before vupdate
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
544
ASSERT(0); // LUT select was updated again before vupdate
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
553
ASSERT(0); // LUT select was updated again before vupdate
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
562
ASSERT(0); // LUT select was updated again before vupdate
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
509
ASSERT(dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
92
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
126
ASSERT(bits_per_channel != 0);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
448
ASSERT(dsc_sink_caps->branch_max_line_width == 0 || dsc_sink_caps->branch_max_line_width >= 5120);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
191
ASSERT(is_config_ok);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
211
ASSERT(is_config_ok);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
232
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
369
ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
370
ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
371
ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
372
ASSERT(dsc_cfg->pic_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
373
ASSERT(dsc_cfg->pic_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
374
ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
379
ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
415
ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
481
ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
98
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
132
ASSERT(is_config_ok);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
151
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
202
ASSERT(!pin->base.opened);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
426
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
445
ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
458
ASSERT(state);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
610
ASSERT(stream_enc_inst < 4 && link_enc_inst < 2);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
643
ASSERT(enc->apg);
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
50
ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
626
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
904
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
300
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
327
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
370
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
108
ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
147
ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
151
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
166
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
153
ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
157
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
90
ASSERT((request_limit & (~0xFFF)) == 0); //field is only 24 bits long
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
91
ASSERT(request_limit > 0); //field is only 24 bits long
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
87
ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
91
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1055
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1104
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1164
ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1169
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &cur_compbuf_size_seg) && !cur_compbuf_size_seg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
990
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1252
ASSERT(param->h_scale_ratio.value);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
176
ASSERT(plane_size->chroma_pitch != 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1042
ASSERT(param->h_scale_ratio.value);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
346
ASSERT(plane_size->chroma_pitch != 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
613
ASSERT(plane_size->chroma_pitch != 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
754
ASSERT(!cur_en || x_pos == 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
755
ASSERT(!cur_en || pos->x_hotspot == 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
775
ASSERT(param->h_scale_ratio.value);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2209
ASSERT(dc->fbc_compressor);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2601
ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
278
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
636
ASSERT(pipe_ctx->stream);
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
60
ASSERT(dc->fbc_compressor);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
198
ASSERT(optc1->max_frame_count != 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2960
ASSERT(new_mpcc != NULL);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3551
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3986
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4008
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1432
ASSERT(i != TIMEOUT_FOR_FLIP_PENDING_US);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1779
ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2064
ASSERT(!pipe->plane_state->triplebuffer_flips);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
235
ASSERT(group_idx != 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2546
ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2547
ASSERT(wb_info->wb_enabled);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2571
ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2670
ASSERT(0); /* VMID cannot be 0 for vm context */
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3012
ASSERT(new_mpcc != NULL);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
430
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
443
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
186
ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
520
ASSERT(new_mpcc != NULL);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1024
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
435
ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
436
ASSERT(wb_info->wb_enabled);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
437
ASSERT(wb_info->mpcc_inst >= 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
438
ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
558
ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
583
ASSERT(stream);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
590
ASSERT(stream_status);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
592
ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
622
ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
856
ASSERT(pipe_ctx->stream);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
383
ASSERT(pipe_ctx->stream);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
523
ASSERT(!pipe_ctx->top_pipe);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
109
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
117
ASSERT(odm_dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
141
ASSERT(odm_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
358
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
79
ASSERT(dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1033
ASSERT(dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1064
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1074
ASSERT(odm_dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1098
ASSERT(odm_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1216
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1621
ASSERT(status == DC_OK);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1657
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1672
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1534
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
336
ASSERT(dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
365
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
373
ASSERT(odm_dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
397
ASSERT(odm_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
455
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
713
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
96
ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
129
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
169
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
178
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
520
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
163
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
190
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
208
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
226
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
242
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
57
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
87
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
52
ASSERT(status == DC_OK);
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
572
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
797
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1263
ASSERT(proposed_table->stream_count -
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1484
ASSERT(proposed_table.stream_count > 0);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1569
ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1592
ASSERT(vc_id == 1);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1599
ASSERT(start_time_slot == 0);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1697
ASSERT(proposed_table.stream_count == 1);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1807
ASSERT(proposed_table.stream_count > 0);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1874
ASSERT(proposed_table.stream_count > 0);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1981
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2356
ASSERT(is_master_pipe_for_link(link, pipe_ctx));
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2472
ASSERT(is_master_pipe_for_link(link, pipe_ctx));
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2492
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
674
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
842
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
113
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
504
ASSERT(av_stream_map_lane_count != 0);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
525
ASSERT(audio_sdp_overhead != 0);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
91
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2220
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2254
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2503
ASSERT(gpio_result == GPIO_RESULT_OK);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
294
ASSERT(dp_cs);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
349
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
379
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
151
ASSERT(link_enc);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1496
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1503
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1597
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
197
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
248
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
849
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
330
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
195
ASSERT(false); /* Message type not supported by helper function. */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
224
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
219
ASSERT(link_dp_get_encoding_format(<_settings->link_settings) ==
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
440
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c
168
ASSERT(*out_data);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
358
ASSERT(link || crtc_timing); // invalid input
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
90
ASSERT(result == DC_OK);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
902
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
111
ASSERT(bp_result == BP_RESULT_NORECORD);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
113
ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
123
ASSERT(mpcc_id < mpc10->num_mpcc);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
136
ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
158
ASSERT(mpc_busy == 0);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
159
ASSERT(mpc_idle == 1);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
192
ASSERT(mpcc_id < mpc10->num_mpcc);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
193
ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
53
ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
476
ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id));
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
500
ASSERT(!mpc_busy);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
501
ASSERT(mpc_idle);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
502
ASSERT(mpc_disabled);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
504
ASSERT(!mpc_disabled);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
505
ASSERT(!mpc_idle);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
534
ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
312
ASSERT(color);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
599
ASSERT(timing != NULL);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
187
ASSERT(opp_cnt == 2);
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
77
ASSERT(timing != NULL);
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
232
ASSERT(opp_cnt == 2 || opp_cnt == 4);
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
55
ASSERT(mem_count_per_opp == 2);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
391
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
159
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
92
ASSERT(total_required == total_allocated);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
439
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
486
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
466
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
399
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
472
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
478
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1090
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
464
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1334
ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1525
ASSERT(next_odm_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1554
ASSERT(!secondary_pipe->bottom_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1561
ASSERT(primary_pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1735
ASSERT(secondary_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1968
ASSERT(0); /* NOT expected yet */
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1977
ASSERT(0); /* NOT expected yet */
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1983
ASSERT(0); /* NOT expected yet */
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2017
ASSERT(pipes);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2056
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2080
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2104
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2155
ASSERT(otg_master);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2265
ASSERT(pipe_count > 0);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
616
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1010
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1287
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
779
ASSERT(pipes);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
835
ASSERT(mpo_pipe->plane_state != pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
856
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
875
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
899
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1439
ASSERT(*lut == NULL && *shaper == NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1542
ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1563
ASSERT(sec_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1569
ASSERT(pri_pipe->bottom_pipe != sec_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1576
ASSERT(pri_pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1641
ASSERT(pipes);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1713
ASSERT(mpo_pipe->plane_state != pipe->plane_state);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1762
ASSERT(0); /* Should never try to merge master pipe */
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1797
ASSERT(hsplit_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1820
ASSERT(pipe_4to1);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1839
ASSERT(pipe_4to1);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2012
ASSERT(dc != NULL && context != NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1265
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1695
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2265
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1323
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1265
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1737
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1260
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1659
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1672
ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1255
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1605
ASSERT(*lut == NULL && *shaper == NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1939
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2001
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2178
ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2181
ASSERT(0); //Entire DCN is harvested!
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2738
ASSERT(0);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2828
ASSERT(opp_head_pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2865
ASSERT(free_pipe->stream_res.dsc);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2872
ASSERT(otg_master);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1236
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1682
ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1685
ASSERT(0); //Entire DCN is harvested!
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1318
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1298
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1299
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1226
ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1864
ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1867
ASSERT(0); //Entire DCN is harvested!
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
668
ASSERT(0);
sys/dev/pci/drm/amd/display/include/fixed31_32.h
212
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
sys/dev/pci/drm/amd/display/include/fixed31_32.h
249
ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
sys/dev/pci/drm/amd/display/include/fixed31_32.h
274
ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
sys/dev/pci/drm/amd/display/include/fixed31_32.h
466
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
sys/dev/pci/drm/amd/display/include/fixed31_32.h
487
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
sys/dev/pci/drm/amd/display/include/fixed31_32.h
522
ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1507
ASSERT(numberof_points > 0);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
174
ASSERT(v_total < stream->timing.v_total);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
209
ASSERT(v_total < stream->timing.v_total);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
1016
ASSERT(0);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
268
ASSERT(lut_index < params.backlight_lut_array_size);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
300
ASSERT(lut_index < params.backlight_lut_array_size);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
970
ASSERT(0);
sys/dev/pci/drm/amd/display/modules/vmid/vmid.c
120
ASSERT(0);
sys/dev/pci/ixgb_ee.c
320
ASSERT(0);
sys/dev/pci/ixgb_hw.c
102
ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
sys/dev/pci/ixgb_hw.c
550
ASSERT(0);
sys/dev/pci/ixgb_hw.c
683
ASSERT(0);
sys/dev/pci/ixgb_hw.c
740
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
sys/dev/pci/ixgb_hw.c
741
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
sys/dev/pci/ixgb_hw.c
742
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
sys/dev/pci/ixgb_hw.c
768
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
sys/dev/pci/ixgb_hw.c
794
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
sys/dev/pci/ixgb_hw.c
827
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
sys/dev/pci/ixgb_hw.c
828
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
sys/dev/pci/ixgb_hw.c
829
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
sys/dev/pci/ixgb_hw.c
858
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
sys/dev/pci/ixgb_hw.c
884
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
usr.sbin/npppd/common/debugmacro.h
36
#ifndef ASSERT
usr.sbin/npppd/common/debugutil.c
131
ASSERT(format != NULL);
usr.sbin/npppd/common/debugutil.c
132
ASSERT(format[0] != '\0');
usr.sbin/npppd/common/debugutil.c
204
ASSERT(0 <= LOG_PRI(prio)
usr.sbin/npppd/common/debugutil.c
84
ASSERT(prio_name[i].prio < countof(prio_name_idx));
usr.sbin/npppd/common/slist_test.c
110
ASSERT((int)slist_get(l, i) == i + f);
usr.sbin/npppd/common/slist_test.c
119
ASSERT((int)slist_get(l, i) == i);
usr.sbin/npppd/common/slist_test.c
127
ASSERT((int)slist_get(l, i) == i);
usr.sbin/npppd/common/slist_test.c
130
ASSERT((int)slist_get(l, slist_length(l) - 1) == 127);
usr.sbin/npppd/common/slist_test.c
134
ASSERT(slist_length(l) == 0);
usr.sbin/npppd/common/slist_test.c
156
ASSERT((int)slist_get(&sl, 127) == 255);
usr.sbin/npppd/common/slist_test.c
157
ASSERT((int)slist_get(&sl, 254) == 129 + 253);
usr.sbin/npppd/common/slist_test.c
158
ASSERT((int)slist_length(&sl) == 255);
usr.sbin/npppd/common/slist_test.c
163
ASSERT((int)slist_get(&sl, 127) == 255);
usr.sbin/npppd/common/slist_test.c
165
ASSERT((int)slist_length(&sl) == 256);
usr.sbin/npppd/common/slist_test.c
192
ASSERT(slist_length(&sl) == 511); /* The logical length is 511. */
usr.sbin/npppd/common/slist_test.c
193
ASSERT((int)sl.list[511] == 211); /* The most right is 211th. */
usr.sbin/npppd/common/slist_test.c
194
ASSERT((int)sl.list[0] == 212); /* The most left is 212th. */
usr.sbin/npppd/common/slist_test.c
195
ASSERT(sl.list_size == 512); /* The physical size is 512. */
usr.sbin/npppd/common/slist_test.c
199
ASSERT(sl.list_size == 768); /* The physical size is extended. */
usr.sbin/npppd/common/slist_test.c
200
ASSERT(slist_length(&sl) == 512); /* The logical length is 512. */
usr.sbin/npppd/common/slist_test.c
201
ASSERT((int)sl.list[511] == 211); /* boundary */
usr.sbin/npppd/common/slist_test.c
202
ASSERT((int)sl.list[512] == 212); /* boundary */
usr.sbin/npppd/common/slist_test.c
203
ASSERT((int)sl.list[767] == 467); /* The most right is 467th. */
usr.sbin/npppd/common/slist_test.c
204
ASSERT((int)sl.list[0] == 468); /* The most left is 468th. */
usr.sbin/npppd/common/slist_test.c
208
ASSERT((int)slist_get(&sl, i) == i + 1); /* check */
usr.sbin/npppd/common/slist_test.c
223
ASSERT(sl.last_idx >= 0 && sl.last_idx < sl.list_size);
usr.sbin/npppd/common/slist_test.c
225
ASSERT(sl.last_idx >= 0 && sl.last_idx < sl.list_size);
usr.sbin/npppd/common/slist_test.c
228
ASSERT(slist_length(&sl) == 0);
usr.sbin/npppd/common/slist_test.c
242
ASSERT((int)slist_itr_next(l) == 1); /* normal iterate */
usr.sbin/npppd/common/slist_test.c
243
ASSERT((int)slist_itr_next(l) == 2); /* normal iterate */
usr.sbin/npppd/common/slist_test.c
245
ASSERT((int)slist_itr_next(l) == 4); /* removed item is skipped */
usr.sbin/npppd/common/slist_test.c
247
ASSERT((int)slist_itr_next(l) == 5); /* no influence */
usr.sbin/npppd/common/slist_test.c
248
ASSERT((int)slist_get(l, 0) == 1); /* checking for removing */
usr.sbin/npppd/common/slist_test.c
249
ASSERT((int)slist_get(l, 1) == 4); /* checking for removing */
usr.sbin/npppd/common/slist_test.c
250
ASSERT((int)slist_get(l, 2) == 5); /* checking for removing */
usr.sbin/npppd/common/slist_test.c
258
ASSERT(slist_itr_next(l) != NULL);
usr.sbin/npppd/common/slist_test.c
259
ASSERT(slist_itr_next(l) != NULL);
usr.sbin/npppd/common/slist_test.c
260
ASSERT(slist_itr_next(l) == NULL);
usr.sbin/npppd/common/slist_test.c
271
ASSERT(slist_length(l) == 253);
usr.sbin/npppd/common/slist_test.c
274
ASSERT(slist_itr_next(l) != NULL);
usr.sbin/npppd/common/slist_test.c
277
ASSERT(slist_itr_next(l) == NULL); /* The last item is NULL */
usr.sbin/npppd/common/slist_test.c
282
ASSERT(slist_length(l) == 0);
usr.sbin/npppd/common/slist_test.c
283
ASSERT(slist_itr_next(l) == NULL);
usr.sbin/npppd/common/slist_test.c
304
ASSERT(slist_length(&sl) == 255);
usr.sbin/npppd/common/slist_test.c
331
ASSERT(sl.first_idx == 254);
usr.sbin/npppd/common/slist_test.c
332
ASSERT(sl.last_idx == 7);
usr.sbin/npppd/common/slist_test.c
335
ASSERT((int)slist_get(l, 0) == 1);
usr.sbin/npppd/common/slist_test.c
336
ASSERT((int)slist_get(l, 1) == 2);
usr.sbin/npppd/common/slist_test.c
337
ASSERT((int)slist_get(l, 2) == 3);
usr.sbin/npppd/common/slist_test.c
338
ASSERT((int)slist_get(l, 3) == 4);
usr.sbin/npppd/common/slist_test.c
339
ASSERT((int)slist_get(l, 4) == 5);
usr.sbin/npppd/common/slist_test.c
340
ASSERT((int)slist_get(l, 5) == 6);
usr.sbin/npppd/common/slist_test.c
341
ASSERT((int)slist_get(l, 6) == 7);
usr.sbin/npppd/common/slist_test.c
342
ASSERT((int)slist_get(l, 7) == 8);
usr.sbin/npppd/common/slist_test.c
343
ASSERT(l->first_idx == 255);
usr.sbin/npppd/common/slist_test.c
346
ASSERT((int)slist_get(l, 0) == 2);
usr.sbin/npppd/common/slist_test.c
347
ASSERT((int)slist_get(l, 1) == 3);
usr.sbin/npppd/common/slist_test.c
348
ASSERT((int)slist_get(l, 2) == 4);
usr.sbin/npppd/common/slist_test.c
349
ASSERT((int)slist_get(l, 3) == 5);
usr.sbin/npppd/common/slist_test.c
350
ASSERT((int)slist_get(l, 4) == 6);
usr.sbin/npppd/common/slist_test.c
351
ASSERT((int)slist_get(l, 5) == 7);
usr.sbin/npppd/common/slist_test.c
352
ASSERT((int)slist_get(l, 6) == 8);
usr.sbin/npppd/common/slist_test.c
353
ASSERT(l->first_idx == 0);
usr.sbin/npppd/common/slist_test.c
370
ASSERT(slist_length(l) == i);
usr.sbin/npppd/common/slist_test.c
372
ASSERT((int)slist_itr_remove(l) == 255 - i);
usr.sbin/npppd/common/slist_test.c
373
ASSERT(slist_length(l) == i - 1);
usr.sbin/npppd/common/slist_test.c
375
ASSERT((int)slist_get(l, j) == i + j);
usr.sbin/npppd/common/slist_test.c
397
ASSERT((int)slist_itr_next(l) == i);
usr.sbin/npppd/common/slist_test.c
399
ASSERT((int)slist_itr_remove(l) == i);
usr.sbin/npppd/common/slist_test.c
425
ASSERT((int)slist_get(l, 0) == 2);
usr.sbin/npppd/common/slist_test.c
426
ASSERT((int)slist_get(l, 1) == 3);
usr.sbin/npppd/common/slist_test.c
427
ASSERT((int)slist_get(l, 2) == 4);
usr.sbin/npppd/common/slist_test.c
431
ASSERT((int)slist_get(l, 0) == 2);
usr.sbin/npppd/common/slist_test.c
432
ASSERT((int)slist_get(l, 1) == 3);
usr.sbin/npppd/common/slist_test.c
433
ASSERT((int)slist_get(l, 2) == 4);
usr.sbin/npppd/common/slist_test.c
434
ASSERT((int)slist_get(l, 3) == 5);
usr.sbin/npppd/common/slist_test.c
453
ASSERT((int)slist_itr_next(l) == 1); /* 1 */
usr.sbin/npppd/common/slist_test.c
454
ASSERT((int)slist_itr_next(l) == 2); /* 2 */
usr.sbin/npppd/common/slist_test.c
455
ASSERT((int)slist_itr_next(l) == 3); /* 3 */
usr.sbin/npppd/common/slist_test.c
458
ASSERT(slist_itr_has_next(l)); /* iterates the new */
usr.sbin/npppd/common/slist_test.c
459
ASSERT((int)slist_itr_next(l) == 4);
usr.sbin/npppd/common/slist_test.c
473
ASSERT((int)slist_itr_next(l) == 1); /* 1 */
usr.sbin/npppd/common/slist_test.c
474
ASSERT((int)slist_itr_next(l) == 2); /* 2 */
usr.sbin/npppd/common/slist_test.c
475
ASSERT((int)slist_itr_next(l) == 3); /* 3 */
usr.sbin/npppd/common/slist_test.c
479
ASSERT(slist_itr_has_next(l)); /* */
usr.sbin/npppd/common/slist_test.c
480
ASSERT((int)slist_itr_next(l) == 4); /* 4 */
usr.sbin/npppd/common/slist_test.c
493
ASSERT((int)slist_itr_next(l) == 1); /* 1 */
usr.sbin/npppd/common/slist_test.c
494
ASSERT((int)slist_itr_next(l) == 2); /* 2 */
usr.sbin/npppd/common/slist_test.c
495
ASSERT((int)slist_itr_next(l) == 3); /* 3 */
usr.sbin/npppd/common/slist_test.c
499
ASSERT(slist_itr_has_next(l));
usr.sbin/npppd/common/slist_test.c
500
ASSERT((int)slist_itr_next(l) == 4); /* 4 */
usr.sbin/npppd/common/slist_test.c
513
ASSERT((int)slist_itr_next(l) == 1); /* 1 */
usr.sbin/npppd/common/slist_test.c
514
ASSERT((int)slist_itr_next(l) == 2); /* 2 */
usr.sbin/npppd/common/slist_test.c
517
ASSERT(slist_itr_has_next(l)); /* iterates the new */
usr.sbin/npppd/common/slist_test.c
518
ASSERT((int)slist_itr_next(l) == 4);
usr.sbin/npppd/common/slist_test.c
533
ASSERT((int)slist_itr_next(l) == 1);
usr.sbin/npppd/common/slist_test.c
534
ASSERT((int)slist_itr_next(l) == 2);
usr.sbin/npppd/common/slist_test.c
536
ASSERT(slist_itr_has_next(l));
usr.sbin/npppd/common/slist_test.c
537
ASSERT((int)slist_itr_next(l) == i - 1);
usr.sbin/npppd/common/slist_test.c
541
ASSERT((int)slist_itr_remove(l) == i - 1);
usr.sbin/npppd/common/slist_test.c
550
ASSERT((int)slist_length(l) == 0);
usr.sbin/npppd/common/slist_test.c
564
ASSERT((int)slist_remove_last(l) == 2);
usr.sbin/npppd/common/slist_test.c
565
ASSERT((int)slist_length(l) == 1);
usr.sbin/npppd/common/slist_test.c
566
ASSERT((int)slist_remove_last(l) == 1);
usr.sbin/npppd/common/slist_test.c
567
ASSERT((int)slist_length(l) == 0);
usr.sbin/npppd/common/slist_test.c
594
ASSERT((int)slist_get(l, 0) == 13);
usr.sbin/npppd/common/slist_test.c
595
ASSERT((int)slist_get(l, 1) == 14);
usr.sbin/npppd/common/slist_test.c
596
ASSERT((int)slist_get(l, 2) == 15);
usr.sbin/npppd/common/slist_test.c
597
ASSERT((int)slist_get(l, 3) == 15);
usr.sbin/npppd/common/slist_test.c
598
ASSERT((int)slist_get(l, 4) == 23);
usr.sbin/npppd/common/slist_test.c
599
ASSERT((int)slist_get(l, 5) == 25);
usr.sbin/npppd/common/slist_test.c
600
ASSERT((int)slist_get(l, 6) == 29);
usr.sbin/npppd/common/slist_test.c
601
ASSERT((int)slist_get(l, 7) == 42);
usr.sbin/npppd/common/slist_test.c
602
ASSERT((int)slist_get(l, 8) == 55);
usr.sbin/npppd/common/slist_test.c
603
ASSERT((int)slist_get(l, 9) == 66);
usr.sbin/npppd/common/slist_test.c
92
ASSERT(sl.list_size == 256);
usr.sbin/npppd/l2tp/l2tp_call.c
1003
ASSERT(_this->ppp == NULL);
usr.sbin/npppd/l2tp/l2tp_call.c
56
#define L2TP_CALL_ASSERT(x) ASSERT(x)
usr.sbin/npppd/l2tp/l2tp_ctrl.c
89
#define L2TP_CTRL_ASSERT(x) ASSERT(x)
usr.sbin/npppd/l2tp/l2tp_subr.c
53
#define L2TP_SUBR_ASSERT(x) ASSERT(x)
usr.sbin/npppd/l2tp/l2tpd.c
65
#define L2TPD_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/ccp.c
49
#define CCP_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/fsm.c
60
#define FSM_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/ipcp.c
53
#define IPCP_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/lcp.c
58
#define LCP_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/npppd.c
121
#define NPPPD_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/npppd_auth_local.h
99
#define NPPPD_AUTH_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/npppd_config.c
59
#define NPPPD_CONFIG_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/npppd_radius.c
61
#define NPPPD_RADIUS_ASSERT(x) ASSERT(x)
usr.sbin/npppd/npppd/npppd_subr.c
146
ASSERT(type == RTM_ADD || type == RTM_DELETE);
usr.sbin/npppd/pppoe/pppoe_session.c
64
#define PPPOE_SESSION_ASSERT(x) ASSERT(x)
usr.sbin/npppd/pppoe/pppoed.c
77
#define PPPOED_ASSERT(x) ASSERT(x)
usr.sbin/npppd/pptp/pptp_call.c
62
#define PPTP_CALL_ASSERT(x) ASSERT(x)
usr.sbin/npppd/pptp/pptp_ctrl.c
67
#define PPTP_CTRL_ASSERT(x) ASSERT(x)
usr.sbin/npppd/pptp/pptpd.c
76
#define PPTPD_ASSERT(x) ASSERT(x)
