sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

319

if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

324

OTG_H_TIMING_DIV_MODE, h_div);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

582

type OTG_H_TIMING_DIV_MODE;\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

211

OTG_H_TIMING_DIV_MODE, h_div);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

270

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

322

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

241

OTG_H_TIMING_DIV_MODE, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

88

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

253

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

101

OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

179

OTG_H_TIMING_DIV_MODE, h_div);

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

250

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

243

OTG_H_TIMING_DIV_MODE, h_div);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

96

OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h

178

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

108

REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

125

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY2);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

144

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

156

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

283

OTG_H_TIMING_DIV_MODE, h_div);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

155

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\