NUM_LINK_LEVELS
for (i = 0; i < NUM_LINK_LEVELS; i++) {
pcie_table->count = NUM_LINK_LEVELS;
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
while (i < NUM_LINK_LEVELS) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
if (soft_min_level >= NUM_LINK_LEVELS ||
soft_max_level >= NUM_LINK_LEVELS)
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++) {
uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
uint8_t PcieLaneCount[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
#define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
uint8_t PcieLaneCount[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 4:PciE-gen5
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++)
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (i = 0; i < NUM_LINK_LEVELS; i++)
for (i = 0; i < NUM_LINK_LEVELS; i++) {
for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {