sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

566

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

571

for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

781

for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

138

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

1022

for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

57

DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

707

for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

77

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

493

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

498

for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

85

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

130

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

118

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

129

DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];