sys/arch/amd64/amd64/intr.c

147

for (level = 0; level < NIPL; level++) {

sys/arch/amd64/amd64/intr.c

155

for (level = 0; level< (NIPL - 1); level++)

sys/arch/amd64/amd64/intr.c

175

for (level = 0; level < NIPL; level++)

sys/arch/amd64/amd64/intr.c

703

for (i = 0; i < NIPL; i++)

sys/arch/amd64/include/cpu.h

157

u_int64_t ci_imask[NIPL];

sys/arch/amd64/include/cpu.h

158

u_int64_t ci_iunmask[NIPL];

sys/arch/arm64/arm64/intr.c

56

uint32_t arm_smask[NIPL];

sys/arch/arm64/dev/aplintc.c

121

TAILQ_HEAD(, intrhand) sc_irq_list[NIPL];

sys/arch/arm64/dev/aplintc.c

265

for (ipl = 0; ipl < NIPL; ipl++)

sys/arch/arm64/dev/bcm2836_intr.c

102

uint32_t sc_imask[INTC_NBANK][NIPL];

sys/arch/arm64/include/intr.h

142

extern uint32_t arm_smask[NIPL];

sys/arch/armv7/armv7/intr.c

51

uint32_t arm_smask[NIPL];

sys/arch/armv7/broadcom/bcm2836_intr.c

97

uint32_t sc_bcm_intc_imask[INTC_NBANK][NIPL];

sys/arch/armv7/include/intr.h

137

extern uint32_t arm_smask[NIPL];

sys/arch/armv7/omap/intc.c

234

INTC_ILR_PRIs(NIPL-max)|INTC_ILR_IRQ);

sys/arch/armv7/omap/intc.c

95

u_int32_t intc_smask[NIPL];

sys/arch/armv7/omap/intc.c

96

u_int32_t intc_imask[INTC_MAX_BANKS][NIPL];

sys/arch/armv7/sunxi/sxiintc.c

135

u_int32_t sxiintc_smask[NIPL];

sys/arch/armv7/sunxi/sxiintc.c

136

u_int32_t sxiintc_imask[NBANKS][NIPL];

sys/arch/armv7/sunxi/sxiintc.c

187

for (j = 0; j < NIPL; j++)

sys/arch/armv7/sunxi/sxiintc.c

251

for (; i < NIPL; i++)

sys/arch/armv7/sunxi/sxiintc.c

38

char *ipl_strtbl[NIPL] = {

sys/arch/hppa/hppa/intr.c

104

for (level = 0; level < NIPL - 1; level++)

sys/arch/hppa/hppa/intr.c

244

for (pri = NIPL - 1; pri > s; pri--) {

sys/arch/hppa/hppa/intr.c

52

volatile u_long imask[NIPL] = {

sys/arch/hppa/include/intr.h

71

extern volatile u_long imask[NIPL];

sys/arch/i386/include/cpu.h

122

u_int32_t ci_imask[NIPL];

sys/arch/i386/include/cpu.h

123

u_int32_t ci_iunmask[NIPL];

sys/arch/i386/isa/isa_machdep.c

237

int imask[NIPL]; /* Bitmask telling what interrupts are blocked. */

sys/arch/i386/isa/isa_machdep.c

238

int iunmask[NIPL]; /* Bitmask telling what interrupts are accepted. */

sys/arch/i386/isa/isa_machdep.c

264

for (level = 0; level < NIPL; level++) {

sys/arch/i386/isa/isa_machdep.c

283

for (level = 0; level < NIPL - 1; level++)

sys/arch/powerpc64/powerpc64/intr.c

68

uint32_t intr_smask[NIPL];

sys/arch/riscv64/include/intr.h

151

extern uint32_t riscv_smask[NIPL];

sys/arch/riscv64/riscv64/intr.c

49

uint32_t riscv_smask[NIPL];