NGBE_WRITE_REG_MASK
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL, NGBE_RSEC_CTL_CRC_STRIP,
NGBE_WRITE_REG_MASK(hw, NGBE_PSR_CTL, NGBE_PSR_CTL_PCSD,
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_TDM_CTL, NGBE_TDM_CTL_TE,
NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_BUF_AE, 0x3ff, 0x10);
NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_CTL, 0x2, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_CTL, 0x1, 1);
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_TX_CFG, NGBE_MAC_TX_CFG_TE,
NGBE_WRITE_REG_MASK(hw, NGBE_MMC_CONTROL, NGBE_MMC_CONTROL_UP,
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG, NGBE_MAC_RX_CFG_RE,
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL, NGBE_RSEC_CTL_RX_DIS,
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG, NGBE_MAC_RX_CFG_RE,
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL, 0x2, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_RDB_PB_CTL, NGBE_RDB_PB_CTL_PBEN,
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL, NGBE_RSEC_CTL_RX_DIS, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_CFG_PORT_CTL,
NGBE_WRITE_REG_MASK(&sc->hw, NGBE_CFG_PORT_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MNG_MBOX_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_SWSM, NGBE_MIS_SWSM_SMBI, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_MNG_SWFW_SYNC, mask, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG, NGBE_MAC_RX_CFG_JE,
NGBE_WRITE_REG_MASK(hw, NGBE_MMC_CONTROL, NGBE_MMC_CONTROL_RSTONRD,
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_FLOW_CTRL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_RST_ST, NGBE_MIS_RST_ST_RST_INIT,
NGBE_WRITE_REG_MASK(hw, NGBE_PSR_MAC_SWC_AD_H,
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_PX_TR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_CFG_PORT_CTL, NGBE_CFG_PORT_CTL_PFRSTD,
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i),
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL,
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_TX_CFG, NGBE_MAC_TX_CFG_TE, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_TDM_CTL, NGBE_TDM_CTL_TE, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_CFG_LAN_SPEED, 0x3, speed);