NGBE_WRITE_REG
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_CTL, vlanctrl);
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, fctrl);
NGBE_WRITE_REG(hw, NGBE_PSR_MAX_SZ, NGBE_MAX_JUMBO_FRAME_SIZE);
NGBE_WRITE_REG(hw, NGBE_PX_RR_BAL(i),
NGBE_WRITE_REG(hw, NGBE_PX_RR_BAH(i), (rdba >> 32));
NGBE_WRITE_REG(hw, NGBE_PX_RR_CFG(i), rxdctl);
NGBE_WRITE_REG(hw, NGBE_PX_RR_RP(i), 0);
NGBE_WRITE_REG(hw, NGBE_PX_RR_WP(i), 0);
NGBE_WRITE_REG(hw, NGBE_PX_RR_CFG(i), srrctl);
NGBE_WRITE_REG(hw, NGBE_PX_RR_WP(i), rxr->last_desc_filled);
NGBE_WRITE_REG(hw, NGBE_RDB_RSSTBL(i >> 2), reta);
NGBE_WRITE_REG(hw, NGBE_RDB_RSSRK(i), rss_key[i]);
NGBE_WRITE_REG(hw, NGBE_RDB_RA_CTL, rss_field);
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), NGBE_PX_TR_CFG_SWFLSH);
NGBE_WRITE_REG(hw, NGBE_PX_TR_BAL(i),
NGBE_WRITE_REG(hw, NGBE_PX_TR_BAH(i), (tdba >> 32));
NGBE_WRITE_REG(hw, NGBE_PX_TR_RP(i), 0);
NGBE_WRITE_REG(hw, NGBE_PX_TR_WP(i), 0);
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), txdctl);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, i);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_L, 0);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_H, 0);
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctl);
NGBE_WRITE_REG(hw, NGBE_PSR_MC_TBL(i), 0);
NGBE_WRITE_REG(hw, NGBE_MDIO_CLAUSE_SELECT, 0xf);
NGBE_WRITE_REG(hw, NGBE_TS_INT_EN, NGBE_TS_INT_EN_DALARM_INT_EN |
NGBE_WRITE_REG(hw, NGBE_TS_EN, NGBE_TS_EN_ENA);
NGBE_WRITE_REG(hw, NGBE_TS_ALARM_THRE, 0x344);
NGBE_WRITE_REG(hw, NGBE_TS_DALARM_THRE, 0x330);
NGBE_WRITE_REG(hw, NGBE_PSR_UC_TBL(i), 0);
NGBE_WRITE_REG(hw, NGBE_MAC_RX_FLOW_CTRL, mflcn);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCC, fccfg);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCL, fcrtl);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCL, 0);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCH, fcrth);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCV, reg);
NGBE_WRITE_REG(hw, NGBE_RDB_RFCRT, hw->fc.pause_time / 2);
NGBE_WRITE_REG(hw, NGBE_SPI_CMD, val);
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_TBL(offset), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC_IDX, offset);
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC, 0);
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC_VM_L, 0);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITRSEL, 0);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITR(nq->msix), newitr);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITR(sc->linkvec), 1950);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_MISC_IEN, 0);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMS, mask);
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctrl);
NGBE_WRITE_REG(hw, NGBE_RDB_PB_CTL, rxctrl);
NGBE_WRITE_REG(hw, NGBE_GPIO_DDR, 0x1);
NGBE_WRITE_REG(hw, NGBE_GPIO_INTEN, 0x3);
NGBE_WRITE_REG(hw, NGBE_GPIO_INTTYPE_LEVEL, 0x0);
NGBE_WRITE_REG(hw, NGBE_GPIO_POLARITY, 0x3);
NGBE_WRITE_REG(hw, NGBE_PX_MISC_IEN, mask);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMC, mask);
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, val);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, 0);
NGBE_WRITE_REG(hw, NGBE_GPIO_EOI, reg);
NGBE_WRITE_REG(hw, NGBE_CALSUM_CAP_STATUS, 0);
NGBE_WRITE_REG(hw, NGBE_EEPROM_VERSION_STORE_REG, 0);
NGBE_WRITE_REG(hw,
NGBE_WRITE_REG(hw,
NGBE_WRITE_REG(hw, NGBE_PHY_CONFIG(off), data);
NGBE_WRITE_REG(hw, NGBE_MNG_SWFW_SYNC, gssr);
NGBE_WRITE_REG(hw, NGBE_MIS_RST,
NGBE_WRITE_REG(hw, NGBE_MAC_PKT_FLT, NGBE_MAC_PKT_FLT_PR);
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_SEL, 0);
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_DW_L(i), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_DW_H(i), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_MSK(i), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_SEL, 0);
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_DW_L(i), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_DW_H(i), 0);
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_MSK(i), 0);
NGBE_WRITE_REG(hw, NGBE_RDB_PFCMACDAL, 0xc2000001);
NGBE_WRITE_REG(hw, NGBE_RDB_PFCMACDAH, 0x0180);
NGBE_WRITE_REG(hw, NGBE_MDIO_CLAUSE_SELECT, 0xf);
NGBE_WRITE_REG(hw, NGBE_PX_MISC_IVAR, ivar);
NGBE_WRITE_REG(hw, NGBE_PX_IVAR(entry >> 1), ivar);
NGBE_WRITE_REG(hw, reg, val);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, index);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_VM, pools & 0xffffffff);
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_L, rar_low);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_CFG(i), srrctl);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_CFG(i), srrctl);
NGBE_WRITE_REG(hw, NGBE_RDB_PB_SZ, rxpktsize);
NGBE_WRITE_REG(hw, NGBE_TDB_PB_SZ, txpktsize);
NGBE_WRITE_REG(hw, NGBE_TDM_PB_THRE, txpbthresh);
NGBE_WRITE_REG(hw, NGBE_PX_GPIE, gpie);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ISB_ADDR_L,
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ISB_ADDR_H, (idba >> 32));
NGBE_WRITE_REG(hw, NGBE_RDB_PL_CFG(0), psrtype);
NGBE_WRITE_REG(hw, NGBE_PX_MISC_IC, 0xffffffff);
NGBE_WRITE_REG(hw, NGBE_BME_CTL, 0x3);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_WP(rxr->me),
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctl);
NGBE_WRITE_REG(hw, NGBE_MAC_TX_CFG,
NGBE_WRITE_REG(&sc->hw, NGBE_PX_TR_WP(txr->me),
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), NGBE_PX_TR_CFG_SWFLSH);
NGBE_WRITE_REG(hw, NGBE_MAC_TX_CFG,
NGBE_WRITE_REG(hw, NGBE_MAC_RX_CFG, reg);
NGBE_WRITE_REG(hw, NGBE_MAC_PKT_FLT, NGBE_MAC_PKT_FLT_PR);
NGBE_WRITE_REG(hw, NGBE_MAC_WDG_TIMEOUT, reg);