NGBE_READ_REG
mhadd = NGBE_READ_REG(hw, NGBE_PSR_MAX_SZ);
rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i));
rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i));
rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i));
rxctrl = NGBE_READ_REG(hw, NGBE_RDB_PB_CTL);
txdctl = NGBE_READ_REG(hw, NGBE_PX_TR_CFG(i));
if (!(NGBE_READ_REG(hw, NGBE_SPI_STATUS) &
psrctl = NGBE_READ_REG(hw, NGBE_PSR_CTL);
mflcn = NGBE_READ_REG(hw, NGBE_MAC_RX_FLOW_CTRL);
fccfg = NGBE_READ_REG(hw, NGBE_RDB_RFCC);
fcrth = NGBE_READ_REG(hw, NGBE_RDB_PB_SZ) - 24576;
if (NGBE_READ_REG(hw, NGBE_SPI_STATUS) & 0x1)
return NGBE_READ_REG(hw, NGBE_SPI_DATA);
if (!(NGBE_READ_REG(hw, NGBE_SPI_STATUS) &
reg = NGBE_READ_REG(hw, NGBE_SPI_ILDR_STATUS);
mmngc = NGBE_READ_REG(&sc->hw, NGBE_MIS_ST);
NGBE_READ_REG(hw, NGBE_RX_CRC_ERROR_FRAMES_LOW);
NGBE_READ_REG(hw, NGBE_RX_LEN_ERROR_FRAMES_LOW);
NGBE_READ_REG(hw, NGBE_RDB_LXONTXC);
NGBE_READ_REG(hw, NGBE_RDB_LXOFFTXC);
NGBE_READ_REG(hw, NGBE_MAC_LXOFFRXC);
NGBE_READ_REG(hw, NGBE_MAC_PXOFFRXC);
NGBE_READ_REG(hw, NGBE_PX_GPRC);
NGBE_READ_REG(hw, NGBE_PX_GPTC);
NGBE_READ_REG(hw, NGBE_PX_GORC_MSB);
NGBE_READ_REG(hw, NGBE_PX_GOTC_MSB);
NGBE_READ_REG(hw, NGBE_RX_BC_FRAMES_GOOD_LOW);
NGBE_READ_REG(hw, NGBE_RX_UNDERSIZE_FRAMES_GOOD);
NGBE_READ_REG(hw, NGBE_RX_OVERSIZE_FRAMES_GOOD);
NGBE_READ_REG(hw, NGBE_RX_FRAME_CNT_GOOD_BAD_LOW);
NGBE_READ_REG(hw, NGBE_TX_FRAME_CNT_GOOD_BAD_LOW);
NGBE_READ_REG(hw, NGBE_TX_MC_FRAMES_GOOD_LOW);
NGBE_READ_REG(hw, NGBE_TX_BC_FRAMES_GOOD_LOW);
NGBE_READ_REG(hw, NGBE_RDM_DRP_PKT);
if (!(NGBE_READ_REG(&sc->hw, NGBE_PX_TRANSACTION_PENDING)))
if (!(NGBE_READ_REG(&sc->hw, NGBE_PX_TRANSACTION_PENDING)))
rxctrl = NGBE_READ_REG(hw, NGBE_RDB_PB_CTL);
psrctrl = NGBE_READ_REG(hw, NGBE_PSR_CTL);
secrxreg = NGBE_READ_REG(hw, NGBE_RSEC_ST);
val = NGBE_READ_REG(hw, NGBE_PSR_CTL);
swsm = NGBE_READ_REG(hw, NGBE_MIS_SWSM);
swsm = NGBE_READ_REG(hw, NGBE_MIS_SWSM);
rar_high = NGBE_READ_REG(hw, NGBE_PSR_MAC_SWC_AD_H);
rar_low = NGBE_READ_REG(hw, NGBE_PSR_MAC_SWC_AD_L);
reg = NGBE_READ_REG(hw, NGBE_GPIO_INTSTATUS);
hicr = NGBE_READ_REG(hw, NGBE_MNG_MBOX_CTL);
eeprom_cksum_devcap = NGBE_READ_REG(hw, NGBE_CALSUM_CAP_STATUS);
hicr = NGBE_READ_REG(hw, NGBE_MNG_MBOX_CTL);
buf[0] = NGBE_READ_REG(hw, NGBE_MNG_MBOX);
rx_pba = NGBE_READ_REG(&sc->hw, NGBE_RDB_PB_SZ) >> NGBE_RDB_PB_SZ_SHIFT;
fwsm = NGBE_READ_REG(hw, NGBE_MIS_ST);
ts_state = NGBE_READ_REG(hw, NGBE_TS_ALARM_ST);
*data = NGBE_READ_REG(hw, NGBE_PHY_CONFIG(off)) & 0xffff;
gssr = NGBE_READ_REG(hw, NGBE_MNG_SWFW_SYNC);
rst_delay = (NGBE_READ_REG(hw, NGBE_MIS_RST_ST) &
NGBE_READ_REG(hw, NGBE_MIS_RST_ST);
reset | NGBE_READ_REG(hw, NGBE_MIS_RST));
val = NGBE_READ_REG(hw, reg);
ivar = NGBE_READ_REG(hw, NGBE_PX_MISC_IVAR);
ivar = NGBE_READ_REG(hw, NGBE_PX_IVAR(entry >> 1));
val = NGBE_READ_REG(hw, reg);
reg = NGBE_READ_REG(hw, NGBE_CFG_PORT_ST);
srrctl = NGBE_READ_REG(&sc->hw, NGBE_PX_RR_CFG(i));
srrctl = NGBE_READ_REG(&sc->hw, NGBE_PX_RR_CFG(i));
psrctl = NGBE_READ_REG(hw, NGBE_PSR_CTL);
(NGBE_READ_REG(hw, NGBE_MAC_TX_CFG) & ~NGBE_MAC_TX_CFG_SPEED_MASK) |
NGBE_READ_REG(hw, NGBE_PX_IC);
NGBE_READ_REG(hw, NGBE_PX_MISC_IC);
rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i));
(NGBE_READ_REG(hw, NGBE_MAC_TX_CFG) &
reg = NGBE_READ_REG(hw, NGBE_MAC_RX_CFG);
reg = NGBE_READ_REG(hw, NGBE_MAC_WDG_TIMEOUT);
NGBE_READ_REG(a, NGBE_MIS_PWR)