ASIC_IS_DCE5
if (ASIC_IS_DCE5(rdev) &&
else if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
!ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev)) {
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev) &&
if (!ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
if (ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev)) {
else if (ASIC_IS_DCE5(rdev))
else if (ASIC_IS_DCE5(rdev))
else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev) &&
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev))
else if (ASIC_IS_DCE5(rdev))
if (ASIC_IS_DCE5(rdev)) {
if (ASIC_IS_DCE5(rdev))