sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

51

[NBIO_HWIP] = "NBIO",

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

223

[NBIO_HWIP] = NBIF_HWID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2597

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2626

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2656

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2673

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2703

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2740

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2772

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2805

adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2918

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4146

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

42

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

39

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

535

if (amdgpu_ip_version(adev, NBIO_HWIP, 0) != IP_VERSION(3, 3, 0))

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

340

if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

280

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

277

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

264

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

371

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

396

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

61

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

80

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

345

if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) &&

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

704

if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

249

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

46

tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));

sys/dev/pci/drm/amd/amdgpu/nv.c

1051

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/soc15.c

1425

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/soc21.c

965

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/soc24.c

544

switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1991

init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];