MV_XLG_PORT_MAC_CTRL0_REG
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG,
mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG) &
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
ctl0 = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, ctl0);
while ((mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG) &
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(port, MV_XLG_PORT_MAC_CTRL0_REG, val);
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);
mvpp2_xlg_write(port, MV_XLG_PORT_MAC_CTRL0_REG, val);