MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
MVPP2_MAX_L3_ADDR_SIZE, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);