sys/arch/amd64/amd64/cacheinfo.c

279

rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 &&

sys/arch/amd64/amd64/cpu.c

1251

rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 &&

sys/arch/amd64/amd64/cpu.c

1254

wrmsr(MSR_MISC_ENABLE, msr);

sys/arch/amd64/amd64/vmm_machdep.c

2372

msr_misc_enable = rdmsr(MSR_MISC_ENABLE);

sys/arch/amd64/amd64/vmm_machdep.c

2390

msr_store[VCPU_HOST_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE;

sys/arch/amd64/amd64/vmm_machdep.c

2404

msr_store[VCPU_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE;

sys/arch/amd64/amd64/vmm_machdep.c

2513

vmx_setmsrbr(vcpu, MSR_MISC_ENABLE);

sys/arch/amd64/amd64/vmm_machdep.c

6056

case MSR_MISC_ENABLE:

sys/arch/amd64/amd64/vmm_machdep.c

8454

case MSR_MISC_ENABLE: return "Misc Enable";

sys/arch/amd64/amd64/vmm_machdep.c

8785

case MSR_MISC_ENABLE: vmm_decode_misc_enable_value(val); break;

sys/arch/i386/i386/machdep.c

1083

if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))

sys/arch/i386/i386/machdep.c

1481

if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))