Symbol: MMHUB_BASE
sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c
36
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c
36
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c
40
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
37
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c
36
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c
36
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
153
.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
152
.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
180
.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
297
.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
144
.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
175
.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
179
.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
186
.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
203
.reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/include/aldebaran_ip_offset.h
126
static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/arct_ip_offset.h
85
static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/beige_goby_ip_offset.h
115
static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/cyan_skillfish_ip_offset.h
79
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/dimgrey_cavefish_ip_offset.h
100
static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/navi10_ip_offset.h
79
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/navi12_ip_offset.h
107
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/navi14_ip_offset.h
107
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/renoir_ip_offset.h
142
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/sienna_cichlid_ip_offset.h
107
static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/vangogh_ip_offset.h
128
static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/vega10_ip_offset.h
146
static const struct IP_BASE __maybe_unused MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/vega20_ip_offset.h
79
static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0, 0 } },
sys/dev/pci/drm/amd/include/yellow_carp_offset.h
103
static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },