Symbol: MPCC_MCM_3DLUT_RAM_SEL
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
744
type MPCC_MCM_3DLUT_RAM_SEL;\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
808
MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
242
SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
279
REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1);