AR_WRITE
AR_WRITE(sc, AR_RXDP, bf->bf_daddr);
AR_WRITE(sc, AR_CR, AR_CR_RXE);
AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr);
AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
AR_WRITE(sc, AR_RC, 0);
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
AR_WRITE(sc, AR_Q_TXE, 1 << qid);
AR_WRITE(sc, AR_PHY_MODE, reg);
AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
AR_WRITE(sc, AR_PHY_TURBO, phy);
AR_WRITE(sc, AR_2040_MODE,
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
AR_WRITE(sc, AR_PHY_TIMING3, reg);
AR_WRITE(sc, AR_PHY_HALFGI, reg);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, 0x7);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, 0x7);
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CCA(i), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
AR_WRITE(sc, AR_PHY_CALMODE, mode);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
AR_WRITE(sc, AR_PHY_POWER_TX_RATE1,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE2,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE3,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE4,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE6,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE7,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE8,
AR_WRITE(sc, AR_PHY_POWER_TX_RATE9,
AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);
AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);
AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);
AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);
AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);
AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);
AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);
AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);
AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
AR_WRITE(sc, AR_PHY(0), 0x00000007);
AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
AR_WRITE(sc, ini->regs[i], val);
AR_WRITE(sc, AR_PHY(68), 0x30002311);
AR_WRITE(sc, AR_PHY_RF_CTL3, 0x0a020001);
AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
AR_WRITE(sc, ini->fastregs[i], pvals[i]);
AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
AR_WRITE(sc, AR_PHY(651), 0x11);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
AR_WRITE(sc, AR_PHY_SFCORR, reg);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
AR_WRITE(sc, AR_PHY_SFCORR, reg);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
AR_WRITE(sc, AR_PHY_TIMING5, reg);
AR_WRITE(sc, AR7010_GPIO_OUT, reg);
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
AR_WRITE(sc, AR_CR, AR_CR_RXE);
AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
AR_WRITE(sc, AR_PHY(0x37), phy);
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
AR_WRITE(sc, AR_PHY_POWER_TX_SUB,
AR_WRITE(sc, AR_PHY_SPUR_REG,
AR_WRITE(sc, AR_PHY_TIMING11,
AR_WRITE(sc, AR_PHY(0), 0x00000007);
AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
AR_WRITE(sc, 0x98b0, 0x1e5795e5);
AR_WRITE(sc, 0x98e0, 0x02008020);
AR_WRITE(sc, 0x98b0, 0x02108421);
AR_WRITE(sc, 0x98ec, 0x00000008);
AR_WRITE(sc, 0x98b0, 0x0e73ff17);
AR_WRITE(sc, 0x98e0, 0x00000420);
AR_WRITE(sc, 0x98f0, 0x01400018);
AR_WRITE(sc, 0x98f0, 0x01c00018);
AR_WRITE(sc, 0x989c, bank6tpc[i]);
AR_WRITE(sc, 0x98d0, 0x0000000f);
AR_WRITE(sc, 0x98d0, 0x0010000f);
AR_WRITE(sc, 0x989c, 0x00000500);
AR_WRITE(sc, 0x989c, 0x00000800);
AR_WRITE(sc, 0x98cc, 0x0000000e);
AR_WRITE(sc, AR_PHY_BB_RFGAIN(i), pvals[i]);
AR_WRITE(sc, 0x989c, rwbank6[i]);
AR_WRITE(sc, 0x98d0, 0x0010000f);
AR_WRITE(sc, 0x989c, pvals[i]);
AR_WRITE(sc, 0x98cc, 0); /* Finalize. */
AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
AR_WRITE(sc, AR_CR, 0);
AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr);
AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr);
AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
AR_WRITE(sc, AR_RC, 0);
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
AR_WRITE(sc, AR_PHY_MODE, reg);
AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
AR_WRITE(sc, AR_PHY_GEN_CTRL, phy);
AR_WRITE(sc, AR_2040_MODE,
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
AR_WRITE(sc, AR_PHY_TIMING3, reg);
AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_SELFGEN_MASK, 0x3);
AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
AR_WRITE(sc, AR_PHY_CCA(i), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
AR_WRITE(sc, AR_PHY_TIMING4, reg);
AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg);
AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg);
AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg);
AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg);
AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg);
AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg);
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg);
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147);
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg);
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg);
AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg);
AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg);
AR_WRITE(sc, AR_PHY_TPC_1, reg);
AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i),
AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg);
AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg);
AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0);
AR_WRITE(sc, AR_PHY_PWRTX_RATE1,
AR_WRITE(sc, AR_PHY_PWRTX_RATE2,
AR_WRITE(sc, AR_PHY_PWRTX_RATE3,
AR_WRITE(sc, AR_PHY_PWRTX_RATE4,
AR_WRITE(sc, AR_PHY_PWRTX_RATE5,
AR_WRITE(sc, AR_PHY_PWRTX_RATE6,
AR_WRITE(sc, AR_PHY_PWRTX_RATE7,
AR_WRITE(sc, AR_PHY_PWRTX_RATE8,
AR_WRITE(sc, AR_PHY_PWRTX_RATE10,
AR_WRITE(sc, AR_PHY_PWRTX_RATE11,
AR_WRITE(sc, AR_PHY_PWRTX_RATE12,
AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]);
AR_WRITE(sc, X(ini->regs[i]), pvals[i]);
AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]);
AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_AGC, reg);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
AR_WRITE(sc, AR_PHY_SFCORR, reg);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
AR_WRITE(sc, AR_PHY_SFCORR, reg);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
AR_WRITE(sc, AR_PHY_TIMING5, reg);
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
AR_WRITE(sc, AR_Q_STATUS_RING_START,
AR_WRITE(sc, AR_Q_STATUS_RING_END,
AR_WRITE(sc, AR_RXBP_THRESH, reg);
AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds));
AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
AR_WRITE(sc, AR_CR, 0);
AR_WRITE(sc, AR_PHY(637), 0x00000000);
AR_WRITE(sc, AR_PHY(638), 0xefff0301);
AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
AR_WRITE(sc, AR_AN_SYNTH9, reg);
AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
AR_WRITE(sc, AR_AN_TOP2, reg);
AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
AR_WRITE(sc, AR_AN_TOP1, reg);
AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
AR_WRITE(sc, AR_PHY_SPUR_REG,
AR_WRITE(sc, AR_PHY_TIMING11,
AR_WRITE(sc, AR_PHY_SFCORR_EXT,
AR_WRITE(sc, prog->regs[i], pvals[i]);
AR_WRITE(sc, prog->regs[i], pvals[i]);
AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
AR_WRITE(sc, AR_PHY_RXGAIN, reg);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
AR_WRITE(sc, AR9285_AN_RF2G4, reg);
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
AR_WRITE(sc, AR9285_AN_RF2G4, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR9285_AN_RF2G8, reg);
AR_WRITE(sc, AR9285_AN_RF2G7, reg);
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
AR_WRITE(sc, regs[i], svg[i]);
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
AR_WRITE(sc, AR9285_AN_RF2G8, reg);
AR_WRITE(sc, AR9285_AN_RF2G7, reg);
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
AR_WRITE(sc, regs[i], svg[i]);
AR_WRITE(sc, AR9285_AN_RF2G3, rf2g3_svg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, 0x6d4000e2);
AR_WRITE(sc, AR_PHY_AGC_CTL1, 0x3139605e);
AR_WRITE(sc, AR_PHY_FIND_SIG, 0x7ec84d2e);
AR_WRITE(sc, AR_PHY_SFCORR_LOW, 0x06903881);
AR_WRITE(sc, AR_PHY_SFCORR, 0x5ac640d0);
AR_WRITE(sc, AR_PHY_CCK_DETECT, 0x803e68c8);
AR_WRITE(sc, AR_PHY_TIMING5, 0xd00a8007);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, 0x05eea6d4);
AR_WRITE(sc, AR9285_AN_RF2G5, reg);
AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg);
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
AR_WRITE(sc, AR_PHY_TPCRG5, reg);
AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + i,
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
AR_WRITE(sc, AR9287_AN_TOP2, reg);
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
AR_WRITE(sc, AR9287_AN_TXPC0, reg);
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_AHB_MODE, reg);
AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0);
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);
AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg);
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);
AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg);
AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);
AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg);
AR_WRITE(sc, addr, val);
AR_WRITE(sc, addr, val); /* Insist. */
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
AR_WRITE(sc, AR_PHY_TIMING11, reg);
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
AR_WRITE(sc, AR_PHY_TIMING11, reg);
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);
AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);
AR_WRITE(sc, AR_PHY_TPC_19, reg);
AR_WRITE(sc, AR_PHY_TPC_18, reg);
AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]));
AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]));
AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]));
AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]));
AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]));
AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CCM);
AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | unicast);
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
AR_WRITE(sc, AR_BT_COEX_MODE,
AR_WRITE(sc, AR_BT_COEX_WEIGHT,
AR_WRITE(sc, AR_BT_COEX_MODE2,
AR_WRITE(sc, AR_GPIO_PDPU, reg);
AR_WRITE(sc, AR_BT_COEX_MODE,
AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0);
AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
AR_WRITE(sc, AR_PHY_ERR_1, 0);
AR_WRITE(sc, AR_PHY_ERR_2, 0);
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base);
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
AR_WRITE(sc, AR_TXCFG, reg);
AR_WRITE(sc, AR_RXCFG, reg);
AR_WRITE(sc, AR_RXFIFO_CFG, 512);
AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
AR_WRITE(sc, AR_TXCFG, reg);
AR_WRITE(sc, AR_CR, AR_CR_RXD);
AR_WRITE(sc, AR_Q_TXD, 1 << qid);
AR_WRITE(sc, AR_QUIET2,
AR_WRITE(sc, AR_QUIET_PERIOD, 100);
AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo);
AR_WRITE(sc, AR_Q_TXD, 0);
AR_WRITE(sc, AR_DRETRY_LIMIT(qid),
AR_WRITE(sc, AR_QMISC(qid),
AR_WRITE(sc, AR_DMISC(qid),
AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),
AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_RSSI_THR, reg);
AR_WRITE(sc, AR_NEXT_DTIM,
AR_WRITE(sc, AR_NEXT_TIM,
AR_WRITE(sc, AR_SLEEP1,
AR_WRITE(sc, AR_SLEEP2,
AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,
AR_WRITE(sc, AR_NEXT_CFP,
AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU);
AR_WRITE(sc, AR_TIMER_MODE,
AR_WRITE(sc, AR_STA_ID1, reg);
AR_WRITE(sc, AR_STA_ID1, reg);
AR_WRITE(sc, AR_STA_ID1, reg);
AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
AR_WRITE(sc, AR_IMR, sc->imask);
AR_WRITE(sc, AR_IMR_S2, mask2);
AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync);
AR_WRITE(sc, AR_IER, 0);
AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
AR_WRITE(sc, AR_IMR, 0);
AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa);
AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210);
AR_WRITE(sc, AR_QOS_NO_ACK,
AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL);
AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff);
AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
AR_WRITE(sc, AR_TSF_L32, tsflo);
AR_WRITE(sc, AR_TSF_U32, tsfhi);
AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]));
AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |
AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
AR_WRITE(sc, AR_BSSMSKU, 0xffff);
AR_WRITE(sc, AR_DEF_ANTENNA, def_ant);
AR_WRITE(sc, AR_BSS_ID0, 0);
AR_WRITE(sc, AR_BSS_ID1, 0);
AR_WRITE(sc, AR_ISR, 0xffffffff);
AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
AR_WRITE(sc, AR_DQCUMASK(i), 1 << i);
AR_WRITE(sc, AR_IMR, sc->imask);
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
AR_WRITE(sc, sc->obs_off, 8);
AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
AR_WRITE(sc, AR_TIMT, SM(AR_TIMT_FIRST, 2000) | SM(AR_TIMT_LAST, 500));
AR_WRITE(sc, AR_MIRT, SM(AR_MIRT_RATE_THRES, 2000));
AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
AR_WRITE(sc, AR_RX_FILTER, reg);
AR_WRITE(sc, AR_DLCL_IFS(qid),
AR_WRITE(sc, AR_DCHNTIME(qid),
AR_WRITE(sc, AR_DCHNTIME(qid), 0);
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, (sifs - 2) * athn_clock_rate(sc));
AR_WRITE(sc, AR_TIME_OUT, reg);
AR_WRITE(sc, AR_TIME_OUT, reg);
AR_WRITE(sc, AR_USEC, reg);
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
AR_WRITE(sc, AR_MCAST_FIL0, lo);
AR_WRITE(sc, AR_MCAST_FIL1, hi);
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
AR_WRITE(sc, AR_FILT_OFDM, 0);
AR_WRITE(sc, AR_FILT_CCK, 0);
AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
AR_WRITE(sc, AR_BSSMSKU, 0xffff);
AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
AR_WRITE(sc, AR_FILT_OFDM, 0);
AR_WRITE(sc, AR_FILT_CCK, 0);
AR_WRITE(sc, AR_MIBC, 0);
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
AR_WRITE(sc, AR_PHY_ERR_1, 0);
AR_WRITE(sc, AR_PHY_ERR_2, 0);
AR_WRITE(sc, AR_RX_FILTER, rfilt);
AR_WRITE(sc, AR_PHY_ERR, reg);
AR_WRITE(sc, AR_PHY_ERR, 0);
AR_WRITE(sc, AR_RTC_FORCE_WAKE,
AR_WRITE(sc, AR_RC, AR_RC_AHB);
AR_WRITE(sc, AR_RTC_RESET, 0);
AR_WRITE(sc, AR_RC, 0);
AR_WRITE(sc, AR_RTC_RESET, 1);
AR_WRITE(sc, AR_RTC_FORCE_WAKE,
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
AR_WRITE(sc, AR_RC, AR_RC_AHB);
AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
AR_WRITE(sc, AR_RTC_RC, 0);
AR_WRITE(sc, AR_RC, 0);
AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
AR_WRITE(sc, AR9271_CLOCK_CONTROL, 0x304);
AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
AR_WRITE(sc, serdes->regs[i], serdes->vals[i]);
AR_WRITE(sc, AR_WA, sc->workaround);
AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
AR_WRITE(sc, AR_FILT_OFDM, 0);
AR_WRITE(sc, AR_FILT_CCK, 0);
AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
AR_WRITE(sc, AR_RX_FILTER, reg);
AR_WRITE(sc, AR_RX_FILTER, reg);
AR_WRITE(sc, AR_CR, AR_CR_RXE);