MMSCH_V1_0_INSERT_DIRECT_WT

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

828

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

831

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

834

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

837

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

839

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

842

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

847

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

849

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

851

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

853

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

854

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

856

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

858

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

860

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

861

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

864

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

881

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

892

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

901

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

905

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

921

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

925

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

926

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

927

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

930

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

234

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

236

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

238

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

242

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

244

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

245

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

246

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

254

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

256

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

259

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

261

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

264

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

267

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

271

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

274

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

277

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

280

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

285

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

289

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

291

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

295

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

297

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);