sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

824

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

868

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

872

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

876

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

909

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

914

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

933

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

243

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

299

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

300

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

305

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

307

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

309

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

317

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1434

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(