MMIO_F
MMIO_F(reg, 4, 0, 0, 0, d, r, w)
MMIO_F(reg, 4, f, 0, 0, d, r, w)
MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8);
MMIO_F(GEN7_L3CNTLREG2, 0x80);
MMIO_F(_MMIO(DMC_MMIO_START_RANGE), 0x3000);
MMIO_F(_MMIO(0x80000), 0x3000);
MMIO_F(SOFT_SCRATCH(0), 16 * 4);
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);
MMIO_F(_MMIO(0x60220), 0x20);
MMIO_F(PCH_GMBUS0, 4 * 4);
MMIO_F(PCH_GPIO_BASE, 6 * 4);
MMIO_F(_MMIO(0xe4f00), 0x28);
#define MMIO_D(reg) MMIO_F(reg, 4)
MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3);
MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3);
MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3);
MMIO_F(_MMIO(0x70400), 0x40);
MMIO_F(_MMIO(0x71400), 0x40);
MMIO_F(_MMIO(0x72400), 0x40);
MMIO_F(prefix(RENDER_RING_BASE), s); \
MMIO_F(_MMIO(0x49090), 0x14);
MMIO_F(_MMIO(0x49190), 0x14);
MMIO_F(_MMIO(0x49290), 0x14);
MMIO_F(prefix(BLT_RING_BASE), s); \
MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);
MMIO_F(prefix(GEN6_BSD_RING_BASE), s); \
MMIO_F(prefix(VEBOX_RING_BASE), s); \
MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50);
MMIO_F(_MMIO(0x64e60), 0x50);
MMIO_F(_MMIO(0x64eC0), 0x50);
MMIO_F(_MMIO(0x64f20), 0x50);
MMIO_F(_MMIO(0x64f80), 0x50);
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s); \
MMIO_F(FENCE_REG_GEN6_LO(0), 0x80);
MMIO_F(_MMIO(0x4f000), 0x90);
MMIO_F(_MMIO(0x5200), 32);
MMIO_F(_MMIO(0x5240), 32);
MMIO_F(_MMIO(0x5280), 16);
MMIO_F(HS_INVOCATION_COUNT, 8);
MMIO_F(DS_INVOCATION_COUNT, 8);
MMIO_F(IA_VERTICES_COUNT, 8);
MMIO_F(IA_PRIMITIVES_COUNT, 8);
MMIO_F(VS_INVOCATION_COUNT, 8);
MMIO_F(GS_INVOCATION_COUNT, 8);
MMIO_F(GS_PRIMITIVES_COUNT, 8);
MMIO_F(CL_INVOCATION_COUNT, 8);
MMIO_F(CL_PRIMITIVES_COUNT, 8);
MMIO_F(PS_INVOCATION_COUNT, 8);
MMIO_F(PS_DEPTH_COUNT, 8);
MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000);
MMIO_F(_MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE);
MMIO_F(LGC_PALETTE(PIPE_A, 0), 1024);
MMIO_F(LGC_PALETTE(PIPE_B, 0), 1024);
MMIO_F(LGC_PALETTE(PIPE_C, 0), 1024);
MMIO_F(_MMIO(0x24d0), 48);
MMIO_F(_MMIO(0x2290), 8);
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);
MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);
MMIO_F(_MMIO(0x70440), 0xc);
MMIO_F(_MMIO(0x71440), 0xc);
MMIO_F(_MMIO(0x72440), 0xc);
MMIO_F(_MMIO(0x7044c), 0xc);
MMIO_F(_MMIO(0x7144c), 0xc);
MMIO_F(_MMIO(0x7244c), 0xc);
MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);
MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);
MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);
MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8);
MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8);
MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8);
MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8);
MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8);