sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

251

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1539

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1645

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1679

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

929

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1571

bbe = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

87

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

429

batch_add(&cmds, MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/intel_lrc.c

100

*regs = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1060

*cs++ = MI_BATCH_BUFFER_END | BIT(15);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1069

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1461

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

124

OUT_BATCH(d, i, MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2757

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3114

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3668

cs[n] = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1771

*h.batch = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

225

*batch++ = MI_BATCH_BUFFER_END; /* not reached */

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

260

*h->batch = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

316

*h.batch = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1047

(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1049

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1205

(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1207

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1370

(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

256

} while (!err && (lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

56

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_rps.c

720

*cancel = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_rps.c

858

*cancel = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

185

*cs = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

612

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

917

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

134

*cmd++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1491

if (*cmd == MI_BATCH_BUFFER_END)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1552

*batch_end = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1557

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/i915_perf.c

2155

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/selftests/i915_request.c

1156

*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */

sys/dev/pci/drm/i915/selftests/i915_request.c

1178

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/selftests/i915_request.c

1438

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/selftests/i915_request.c

976

*cmd = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/selftests/igt_spinner.c

197

*batch++ = MI_BATCH_BUFFER_END; /* not reached */

sys/dev/pci/drm/i915/selftests/igt_spinner.c

233

*spin->batch = MI_BATCH_BUFFER_END;