MIPI_CTRL
tmp = intel_de_read(display, MIPI_CTRL(display, port));
tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
intel_de_write(display, MIPI_CTRL(display, PORT_A),
tmp = intel_de_read(display, MIPI_CTRL(display, port));
intel_de_write(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
intel_de_rmw(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);
intel_de_rmw(display, MIPI_CTRL(display, port),
u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
temp = intel_de_read(display, MIPI_CTRL(display, port));
intel_de_write(display, MIPI_CTRL(display, port),