Symbol: GC_EDC_CTRL__EDC_LEVEL_SEL_MASK
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
20789
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00004000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
18878
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00004000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
25408
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
27923
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h
21470
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h
7854
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
6733
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x40000000L