sys/dev/pci/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

3666

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

55999

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33903

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39837

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75272

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101535

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44477

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3649

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0