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regIA_UTCL1_STATUS_2
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
2056
#define regIA_UTCL1_STATUS_2 0x0fd7
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
2118
#define regIA_UTCL1_STATUS_2 0x0fd7
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
2214
#define regIA_UTCL1_STATUS_2 0x0fd7
