Symbol: mmUVD_MPC_SET_MUXA1_BASE_IDX
sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
169
#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
349
#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
599
#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
764
#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
1144
#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1