Symbol: mmSQ_UTCL1_CNTL2_BASE_IDX
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
426
#define mmSQ_UTCL1_CNTL2_BASE_IDX 0
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
420
#define mmSQ_UTCL1_CNTL2_BASE_IDX 0
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
416
#define mmSQ_UTCL1_CNTL2_BASE_IDX 0