sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

66

#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

90

#define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

64

#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

70

#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

86

#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

186

#define mmUVD_VCPU_CACHE_OFFSET2 0x0586

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

372

#define mmUVD_VCPU_CACHE_OFFSET2 0x0586

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

622

#define mmUVD_VCPU_CACHE_OFFSET2 0x0246

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

693

#define mmUVD_VCPU_CACHE_OFFSET2 0x0144

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1069

#define mmUVD_VCPU_CACHE_OFFSET2 0x0144