sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

38

#define mmUVD_SEMA_CNTL 0x3d00

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

78

#define mmUVD_SEMA_CNTL 0x3D00

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

38

#define mmUVD_SEMA_CNTL 0x3d00

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

44

#define mmUVD_SEMA_CNTL 0x3d00

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

55

#define mmUVD_SEMA_CNTL 0x3d00

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

122

#define mmUVD_SEMA_CNTL 0x0500

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

248

#define mmUVD_SEMA_CNTL 0x0500

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

476

#define mmUVD_SEMA_CNTL 0x01c0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

815

#define mmUVD_SEMA_CNTL 0x02ef

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1201

#define mmUVD_SEMA_CNTL 0x02ef