Symbol: mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
7664
#define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
7295
#define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX 1