sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

30

#define mmUVD_GPCOM_VCPU_CMD 0x3bc3

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

42

#define mmUVD_GPCOM_VCPU_CMD 0x3BC3

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

30

#define mmUVD_GPCOM_VCPU_CMD 0x3bc3

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

30

#define mmUVD_GPCOM_VCPU_CMD 0x3bc3

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

30

#define mmUVD_GPCOM_VCPU_CMD 0x3bc3

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

54

#define mmUVD_GPCOM_VCPU_CMD 0x03c3

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

138

#define mmUVD_GPCOM_VCPU_CMD 0x03c3

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

810

#define mmUVD_GPCOM_VCPU_CMD 0x0583

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

511

#define mmUVD_GPCOM_VCPU_CMD 0x008f

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

827

#define mmUVD_GPCOM_VCPU_CMD 0x008f