Symbol: mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
9558
#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
9394
#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
6222
#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
6444
#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
6420
#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1