sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

41

#define mmSDMA0_POWER_CNTL 0x001a

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

48

#define mmSDMA0_POWER_CNTL 0x001a

sys/dev/pci/drm/amd/include/asic_reg/oss/oss_2_0_d.h

221

#define mmSDMA0_POWER_CNTL 0x3402

sys/dev/pci/drm/amd/include/asic_reg/oss/oss_2_4_d.h

159

#define mmSDMA0_POWER_CNTL 0x3402

sys/dev/pci/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

156

#define mmSDMA0_POWER_CNTL 0x3402

sys/dev/pci/drm/amd/include/asic_reg/oss/oss_3_0_d.h

293

#define mmSDMA0_POWER_CNTL 0x3402

sys/dev/pci/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

66

#define mmSDMA0_POWER_CNTL 0x001a

sys/dev/pci/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h

64

#define mmSDMA0_POWER_CNTL 0x001a

sys/dev/pci/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h

66

#define mmSDMA0_POWER_CNTL 0x001a

sys/dev/pci/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h

66

#define mmSDMA0_POWER_CNTL 0x001a