Symbol: mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
4964
#define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
4621
#define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0