Symbol: mmCP_GFX_HQD_HQ_CONTROL0
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
5055
#define mmCP_GFX_HQD_HQ_CONTROL0 0x1e99
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
4712
#define mmCP_GFX_HQD_HQ_CONTROL0 0x1e99