sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h

8918

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0xf

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h

8549

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h

8286

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h

8270

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h

8247

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h

8140

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h

8970

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h

16523

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h

6895

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h

9627

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h

5917

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h

5919

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h

11920

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h

11899

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h

7332

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10

sys/dev/pci/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h

6155

#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10