sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

69

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1505

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1508

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2946

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2039

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6332

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7136

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6159

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L