sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

63

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1499

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1502

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2940

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2033

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6326

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7130

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6153

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L