sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

751

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

240

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

468

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3223

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2097

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3768

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2833

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1350

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1350

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1346

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1155

#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L