sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

745

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

747

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

237

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

465

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3220

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2094

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3765

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2830

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1347

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1347

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1343

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1152

#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L