sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

763

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

746

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

749

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2578

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

908

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

5289

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

5115

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

4693

#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L