sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

97

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1553

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1556

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2994

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2102

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6383

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7199

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6216

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5393

#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L