sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1541

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1544

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2982

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2078

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6360

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7164

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6187

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5364

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L