sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

132

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

95

#define UVD_CGC_GATE__RBC__SHIFT 0x00000004

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

132

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

144

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

146

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

381

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

809

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1827

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1879

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3550

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2609

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

38

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

38

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

34

#define UVD_CGC_GATE__RBC__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

38

#define UVD_CGC_GATE__RBC__SHIFT 0x4